net/e1000/base: support more I219 devices

[dpdk.git] / drivers / net / e1000 / base / e1000_ich8lan.c

diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c
index 7ab0f7c..6dd046d 100644 (file)
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -346,6 +346,7 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
        switch (hw->mac.type) {
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;
 
@@ -494,6 +495,7 @@ STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
                case e1000_pch2lan:
                case e1000_pch_lpt:
                case e1000_pch_spt:
+               case e1000_pch_cnp:
                        /* In case the PHY needs to be in mdio slow mode,
                         * set slow mode and try to get the PHY id again.
                         */
@@ -798,6 +800,7 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
                /* fall-through */
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
                /* multicast address update for pch2 */
                mac->ops.update_mc_addr_list =
@@ -1584,6 +1587,16 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                        hw->phy.ops.write_reg_locked(hw,
                                                     I217_PLL_CLOCK_GATE_REG,
                                                     phy_reg);
+
+                       if (speed == SPEED_1000) {
+                               hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
+                                                           &phy_reg);
+
+                               phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
+
+                               hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
+                                                            phy_reg);
+                               }
                 }
                hw->phy.ops.release(hw);
 
@@ -1678,6 +1691,9 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                                fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
                }
 
+               if (hw->dev_spec.ich8lan.disable_k1_off == true)
+                       fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
+
                E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
        }
 
@@ -1775,6 +1791,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
        case e1000_pch2lan:
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
                break;
        default:
@@ -2241,6 +2258,7 @@ STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
        case e1000_pch2lan:
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
                break;
        default:
@@ -3365,6 +3383,7 @@ STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 
        switch (hw->mac.type) {
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                bank1_offset = nvm->flash_bank_size;
                act_offset = E1000_ICH_NVM_SIG_WORD;
 
@@ -4340,6 +4359,7 @@ STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
        switch (hw->mac.type) {
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                word = NVM_COMPAT;
                valid_csum_mask = NVM_COMPAT_VALID_CSUM;
                break;