net/mlx5: add flow match on GENEVE item

[dpdk.git] / drivers / net / e1000 / base / e1000_ich8lan.c

diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c
index 89265d2..accc6ea 100644 (file)
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -1,35 +1,6 @@
-/*******************************************************************************
-
-Copyright (c) 2001-2015, Intel Corporation
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-
- 3. Neither the name of the Intel Corporation nor the names of its
-    contributors may be used to endorse or promote products derived from
-    this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-
-***************************************************************************/
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001 - 2015 Intel Corporation
+ */
 
 /* 82562G 10/100 Network Connection
  * 82562G-2 10/100 Network Connection
@@ -346,6 +317,7 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
        switch (hw->mac.type) {
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;
 
@@ -494,6 +466,7 @@ STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
                case e1000_pch2lan:
                case e1000_pch_lpt:
                case e1000_pch_spt:
+               case e1000_pch_cnp:
                        /* In case the PHY needs to be in mdio slow mode,
                         * set slow mode and try to get the PHY id again.
                         */
@@ -798,6 +771,7 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
                /* fall-through */
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
                /* multicast address update for pch2 */
                mac->ops.update_mc_addr_list =
@@ -1688,6 +1662,9 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                                fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
                }
 
+               if (hw->dev_spec.ich8lan.disable_k1_off == true)
+                       fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
+
                E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
        }
 
@@ -1785,6 +1762,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
        case e1000_pch2lan:
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
                break;
        default:
@@ -2251,6 +2229,7 @@ STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
        case e1000_pch2lan:
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
                break;
        default:
@@ -3375,6 +3354,7 @@ STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 
        switch (hw->mac.type) {
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                bank1_offset = nvm->flash_bank_size;
                act_offset = E1000_ICH_NVM_SIG_WORD;
 
@@ -4350,6 +4330,7 @@ STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
        switch (hw->mac.type) {
        case e1000_pch_lpt:
        case e1000_pch_spt:
+       case e1000_pch_cnp:
                word = NVM_COMPAT;
                valid_csum_mask = NVM_COMPAT_VALID_CSUM;
                break;
@@ -4878,7 +4859,7 @@ STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
  *  @hw: pointer to the HW structure
  *
  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
- *  register, so the the bus width is hard coded.
+ *  register, so the bus width is hard coded.
  **/
 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
 {
@@ -5156,7 +5137,7 @@ STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
        /* Device Status */
        if (hw->mac.type == e1000_ich8lan) {
                reg = E1000_READ_REG(hw, E1000_STATUS);
-               reg &= ~(1 << 31);
+               reg &= ~(1U << 31);
                E1000_WRITE_REG(hw, E1000_STATUS, reg);
        }