net/e1000/base: expose more future extended NVM

[dpdk.git] / drivers / net / e1000 / base / e1000_ich8lan.c

diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c
index 823dda5..b79e3ba 100644 (file)
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -1268,6 +1268,7 @@ out:
 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
 {
        s32 ret_val = E1000_SUCCESS;
+       u8 ulp_exit_timeout = 30;
        u32 mac_reg;
        u16 phy_reg;
        int i = 0;
@@ -1289,10 +1290,12 @@ s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
                        E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
                }
 
-               /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
+               if (hw->mac.type == e1000_pch_cnp)
+                       ulp_exit_timeout = 100;
+
                while (E1000_READ_REG(hw, E1000_FWSM) &
                       E1000_FWSM_ULP_CFG_DONE) {
-                       if (i++ == 30) {
+                       if (i++ == ulp_exit_timeout) {
                                ret_val = -E1000_ERR_PHY;
                                goto out;
                        }
@@ -4896,6 +4899,7 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
        u16 kum_cfg;
        u32 ctrl, reg;
        s32 ret_val;
+       u16 pci_cfg;
 
        DEBUGFUNC("e1000_reset_hw_ich8lan");
 
@@ -4956,11 +4960,28 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
                        e1000_gate_hw_phy_config_ich8lan(hw, true);
        }
        ret_val = e1000_acquire_swflag_ich8lan(hw);
+
+       /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
+        * may occur during global reset and cause system hang.
+        * Configuration space access creates the needed delay.
+        * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
+        * insures configuration space read is done before global reset.
+        */
+       e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
+       E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
        DEBUGOUT("Issuing a global reset to ich8lan\n");
        E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
        /* cannot issue a flush here because it hangs the hardware */
        msec_delay(20);
 
+       /* Configuration space access improve HW level time sync mechanism.
+        * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
+        * value to insure configuration space read is done
+        * before any access to mac register.
+        */
+       e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
+       E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
+
        /* Set Phy Config Counter to 50msec */
        if (hw->mac.type == e1000_pch2lan) {
                reg = E1000_READ_REG(hw, E1000_FEXTNVM3);