net/e1000/base: add missing device ID

[dpdk.git] / drivers / net / e1000 / base / e1000_ich8lan.c

diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c
index accc6ea..b79e3ba 100644 (file)
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -822,7 +822,7 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 /**
  *  __e1000_access_emi_reg_locked - Read/write EMI register
  *  @hw: pointer to the HW structure
- *  @addr: EMI address to program
+ *  @address: EMI address to program
  *  @data: pointer to value to read/write from/to the EMI address
  *  @read: boolean flag to indicate read or write
  *
@@ -1268,6 +1268,7 @@ out:
 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
 {
        s32 ret_val = E1000_SUCCESS;
+       u8 ulp_exit_timeout = 30;
        u32 mac_reg;
        u16 phy_reg;
        int i = 0;
@@ -1289,10 +1290,12 @@ s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
                        E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
                }
 
-               /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
+               if (hw->mac.type == e1000_pch_cnp)
+                       ulp_exit_timeout = 100;
+
                while (E1000_READ_REG(hw, E1000_FWSM) &
                       E1000_FWSM_ULP_CFG_DONE) {
-                       if (i++ == 30) {
+                       if (i++ == ulp_exit_timeout) {
                                ret_val = -E1000_ERR_PHY;
                                goto out;
                        }
@@ -1546,8 +1549,6 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 
 
                if (hw->mac.type >= e1000_pch_lpt) {
-                       u16 phy_reg;
-
                        hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
                                                    &phy_reg);
                        phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
@@ -2401,7 +2402,7 @@ release:
 /**
  *  e1000_configure_k1_ich8lan - Configure K1 power state
  *  @hw: pointer to the HW structure
- *  @enable: K1 state to configure
+ *  @k1_enable: K1 state to configure
  *
  *  Configure the K1 power state based on the provided parameter.
  *  Assumes semaphore already acquired.
@@ -2549,6 +2550,7 @@ STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
 /**
  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
  *  done after every PHY reset.
+ *  @hw: pointer to the HW structure
  **/
 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 {
@@ -2875,6 +2877,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
 /**
  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
  *  done after every PHY reset.
+ *  @hw: pointer to the HW structure
  **/
 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 {
@@ -3479,8 +3482,9 @@ STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
 
        for (i = 0; i < words; i += 2) {
                if (words - i == 1) {
-                       if (dev_spec->shadow_ram[offset+i].modified) {
-                               data[i] = dev_spec->shadow_ram[offset+i].value;
+                       if (dev_spec->shadow_ram[offset + i].modified) {
+                               data[i] =
+                                   dev_spec->shadow_ram[offset + i].value;
                        } else {
                                offset_to_read = act_offset + i -
                                                 ((act_offset + i) % 2);
@@ -3497,8 +3501,8 @@ STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
                        }
                } else {
                        offset_to_read = act_offset + i;
-                       if (!(dev_spec->shadow_ram[offset+i].modified) ||
-                           !(dev_spec->shadow_ram[offset+i+1].modified)) {
+                       if (!(dev_spec->shadow_ram[offset + i].modified) ||
+                           !(dev_spec->shadow_ram[offset + i + 1].modified)) {
                                ret_val =
                                   e1000_read_flash_dword_ich8lan(hw,
                                                                 offset_to_read,
@@ -3506,15 +3510,16 @@ STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
                                if (ret_val)
                                        break;
                        }
-                       if (dev_spec->shadow_ram[offset+i].modified)
-                               data[i] = dev_spec->shadow_ram[offset+i].value;
+                       if (dev_spec->shadow_ram[offset + i].modified)
+                               data[i] =
+                                   dev_spec->shadow_ram[offset + i].value;
                        else
-                               data[i] = (u16) (dword & 0xFFFF);
-                       if (dev_spec->shadow_ram[offset+i].modified)
-                               data[i+1] =
-                                  dev_spec->shadow_ram[offset+i+1].value;
+                               data[i] = (u16)(dword & 0xFFFF);
+                       if (dev_spec->shadow_ram[offset + i + 1].modified)
+                               data[i + 1] =
+                                  dev_spec->shadow_ram[offset + i + 1].value;
                        else
-                               data[i+1] = (u16) (dword >> 16 & 0xFFFF);
+                               data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
                }
        }
 
@@ -3568,8 +3573,8 @@ STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
 
        ret_val = E1000_SUCCESS;
        for (i = 0; i < words; i++) {
-               if (dev_spec->shadow_ram[offset+i].modified) {
-                       data[i] = dev_spec->shadow_ram[offset+i].value;
+               if (dev_spec->shadow_ram[offset + i].modified) {
+                       data[i] = dev_spec->shadow_ram[offset + i].value;
                } else {
                        ret_val = e1000_read_flash_word_ich8lan(hw,
                                                                act_offset + i,
@@ -3974,8 +3979,8 @@ STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
        nvm->ops.acquire(hw);
 
        for (i = 0; i < words; i++) {
-               dev_spec->shadow_ram[offset+i].modified = true;
-               dev_spec->shadow_ram[offset+i].value = data[i];
+               dev_spec->shadow_ram[offset + i].modified = true;
+               dev_spec->shadow_ram[offset + i].value = data[i];
        }
 
        nvm->ops.release(hw);
@@ -4894,6 +4899,7 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
        u16 kum_cfg;
        u32 ctrl, reg;
        s32 ret_val;
+       u16 pci_cfg;
 
        DEBUGFUNC("e1000_reset_hw_ich8lan");
 
@@ -4954,11 +4960,28 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
                        e1000_gate_hw_phy_config_ich8lan(hw, true);
        }
        ret_val = e1000_acquire_swflag_ich8lan(hw);
+
+       /* Read from EXTCNF_CTRL in e1000_acquire_swflag_ich8lan function
+        * may occur during global reset and cause system hang.
+        * Configuration space access creates the needed delay.
+        * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER value
+        * insures configuration space read is done before global reset.
+        */
+       e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
+       E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
        DEBUGOUT("Issuing a global reset to ich8lan\n");
        E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
        /* cannot issue a flush here because it hangs the hardware */
        msec_delay(20);
 
+       /* Configuration space access improve HW level time sync mechanism.
+        * Write to E1000_STRAP RO register E1000_PCI_VENDOR_ID_REGISTER
+        * value to insure configuration space read is done
+        * before any access to mac register.
+        */
+       e1000_read_pci_cfg(hw, E1000_PCI_VENDOR_ID_REGISTER, &pci_cfg);
+       E1000_WRITE_REG(hw, E1000_STRAP, pci_cfg);
+
        /* Set Phy Config Counter to 50msec */
        if (hw->mac.type == e1000_pch2lan) {
                reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
@@ -5533,7 +5556,7 @@ void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
 {
        s32 ret_val;
-       u16 reg_data;
+       u16 reg_data = 0;
 
        DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");