net/e1000/base: define max Rx jumbo frame size

[dpdk.git] / drivers / net / e1000 / base / e1000_ich8lan.h

diff --git a/drivers/net/e1000/base/e1000_ich8lan.h b/drivers/net/e1000/base/e1000_ich8lan.h
index 97da6bf..6aa9288 100644 (file)
--- a/drivers/net/e1000/base/e1000_ich8lan.h
+++ b/drivers/net/e1000/base/e1000_ich8lan.h
@@ -114,7 +114,10 @@ POSSIBILITY OF SUCH DAMAGE.
 
 #define E1000_FEXTNVM6_REQ_PLL_CLK     0x00000100
 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION       0x00000200
-
+#define E1000_FEXTNVM6_K1_OFF_ENABLE   0x80000000
+/* bit for disabling packet buffer read */
+#define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000
+#define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004
 #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
 #define E1000_FEXTNVM7_DISABLE_SMB_PERST       0x00000020
 #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
@@ -179,6 +182,8 @@ POSSIBILITY OF SUCH DAMAGE.
 
 #define E1000_NVM_K1_CONFIG    0x1B /* NVM K1 Config Word */
 #define E1000_NVM_K1_ENABLE    0x1  /* NVM Enable K1 bit */
+#define K1_ENTRY_LATENCY       0
+#define K1_MIN_TIME            1
 
 /* SMBus Control Phy Register */
 #define CV_SMB_CTRL            PHY_REG(769, 23)
@@ -232,6 +237,9 @@ POSSIBILITY OF SUCH DAMAGE.
 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
 #define HV_PM_CTRL_K1_ENABLE           0x4000
 
+#define I217_PLL_CLOCK_GATE_REG        PHY_REG(772, 28)
+#define I217_PLL_CLOCK_GATE_MASK       0x07FF
+
 #define SW_FLAG_TIMEOUT                1000 /* SW Semaphore flag timeout in ms */
 
 /* Inband Control */
@@ -261,12 +269,14 @@ POSSIBILITY OF SUCH DAMAGE.
 #define I82577_MSE_THRESHOLD   0x0887 /* 82577 Mean Square Error Threshold */
 #define I82579_MSE_LINK_DOWN   0x2411 /* MSE count before dropping link */
 #define I82579_RX_CONFIG               0x3412 /* Receive configuration */
+#define I82579_LPI_PLL_SHUT            0x4412 /* LPI PLL Shut Enable */
 #define I82579_EEE_PCS_STATUS          0x182E  /* IEEE MMD Register 3.1 >> 8 */
 #define I82579_EEE_CAPABILITY          0x0410 /* IEEE MMD Register 3.20 */
 #define I82579_EEE_ADVERTISEMENT       0x040E /* IEEE MMD Register 7.60 */
 #define I82579_EEE_LP_ABILITY          0x040F /* IEEE MMD Register 7.61 */
 #define I82579_EEE_100_SUPPORTED       (1 << 1) /* 100BaseTx EEE */
 #define I82579_EEE_1000_SUPPORTED      (1 << 2) /* 1000BaseTx EEE */
+#define I82579_LPI_100_PLL_SHUT        (1 << 2) /* 100M LPI PLL Shut Enabled */
 #define I217_EEE_PCS_STATUS    0x9401   /* IEEE MMD Register 3.1 */
 #define I217_EEE_CAPABILITY    0x8000   /* IEEE MMD Register 3.20 */
 #define I217_EEE_ADVERTISEMENT 0x8001   /* IEEE MMD Register 7.60 */
@@ -299,6 +309,7 @@ void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
+s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time);
 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);