crypto/octeontx: add session management operations
[dpdk.git] / drivers / net / e1000 / base / e1000_phy.h
index 2b78af0..2cd0e14 100644 (file)
@@ -274,6 +274,13 @@ bool e1000_is_mphy_ready(struct e1000_hw *hw);
 #define E1000_KMRNCTRLSTA_K1_CONFIG    0x7
 #define E1000_KMRNCTRLSTA_K1_ENABLE    0x0002 /* enable K1 */
 #define E1000_KMRNCTRLSTA_HD_CTRL      0x10   /* Kumeran HD Control */
+#define E1000_KMRNCTRLSTA_K0S_CTRL     0x1E    /* Kumeran K0s Control */
+#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT   0
+#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT      4
+#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK    \
+       (3 << E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)
+#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \
+       (7 << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)
 #define E1000_KMRNCTRLSTA_OP_MODES     0x1F   /* Kumeran Modes of Operation */
 #define E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC     0x0002 /* change LSC to CSC */
 
@@ -323,4 +330,12 @@ struct sfp_e1000_flags {
 #define E1000_SFF_VENDOR_OUI_AVAGO     0x00176A00
 #define E1000_SFF_VENDOR_OUI_INTEL     0x001B2100
 
+/* EEPROM byte offsets */
+#define IGB_SFF_8472_SWAP              0x5C
+#define IGB_SFF_8472_COMP              0x5E
+
+/* Bitmasks */
+#define IGB_SFF_ADDRESSING_MODE        0x4
+#define IGB_SFF_8472_UNSUP             0x00
+
 #endif