net/e1000/base: add missing device ID

[dpdk.git] / drivers / net / e1000 / base / e1000_regs.h

diff --git a/drivers/net/e1000/base/e1000_regs.h b/drivers/net/e1000/base/e1000_regs.h
index b072c5c..4af9e17 100644 (file)
--- a/drivers/net/e1000/base/e1000_regs.h
+++ b/drivers/net/e1000/base/e1000_regs.h
@@ -138,7 +138,10 @@
 #define E1000_RADV     0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
 #define E1000_EMIADD   0x10     /* Extended Memory Indirect Address */
 #define E1000_EMIDATA  0x11     /* Extended Memory Indirect Data */
-#define E1000_SRWR             0x12018  /* Shadow Ram Write Register - RW */
+/* Shadow Ram Write Register - RW */
+#define E1000_SRWR             0x12018
+#define E1000_EEC_REG          0x12010
+
 #define E1000_I210_FLMNGCTL    0x12038
 #define E1000_I210_FLMNGDATA   0x1203C
 #define E1000_I210_FLMNGCNT    0x12040
@@ -149,6 +152,9 @@
 
 #define E1000_I210_FLA         0x1201C
 
+#define E1000_SHADOWINF                0x12068
+#define E1000_FLFWUPDATE       0x12108
+
 #define E1000_INVM_DATA_REG(_n)        (0x12120 + 4*(_n))
 #define E1000_INVM_SIZE                64 /* Number of INVM Data Registers */
 
@@ -283,6 +289,7 @@
 #define E1000_TIDV     0x03820  /* Tx Interrupt Delay Value - RW */
 #define E1000_TADV     0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
 #define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
+/* Statistics Register Descriptions */
 #define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
 #define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
 #define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
@@ -484,17 +491,20 @@
 #define E1000_MANC2H           0x05860 /* Management Control To Host - RW */
 /* Management Decision Filters */
 #define E1000_MDEF(_n)         (0x05890 + (4 * (_n)))
+/* Semaphore registers */
 #define E1000_SW_FW_SYNC       0x05B5C /* SW-FW Synchronization - RW */
 #define E1000_CCMCTL   0x05B48 /* CCM Control Register */
 #define E1000_GIOCTL   0x05B44 /* GIO Analog Control Register */
 #define E1000_SCCTL    0x05B4C /* PCIc PLL Configuration Register */
+/* PCIe Register Description */
 #define E1000_GCR      0x05B00 /* PCI-Ex Control */
 #define E1000_GCR2     0x05B64 /* PCI-Ex Control #2 */
 #define E1000_GSCL_1   0x05B10 /* PCI-Ex Statistic Control #1 */
 #define E1000_GSCL_2   0x05B14 /* PCI-Ex Statistic Control #2 */
 #define E1000_GSCL_3   0x05B18 /* PCI-Ex Statistic Control #3 */
 #define E1000_GSCL_4   0x05B1C /* PCI-Ex Statistic Control #4 */
-#define E1000_FACTPS   0x05B30 /* Function Active and Power State to MNG */
+/* Function Active and Power State to MNG */
+#define E1000_FACTPS   0x05B30
 #define E1000_SWSM     0x05B50 /* SW Semaphore */
 #define E1000_FWSM     0x05B54 /* FW Semaphore */
 /* Driver-only SW semaphore (not used by BOOT agents) */
@@ -513,8 +523,10 @@
 #define E1000_IMIREXT(_i)      (0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/
 #define E1000_IMIRVP           0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
 #define E1000_MSIXBM(_i)       (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
-#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
-#define E1000_RSSRK(_i)        (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
+/* Redirection Table - RW Array */
+#define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
+/* RSS Random Key - RW Array */
+#define E1000_RSSRK(_i)        (0x05C80 + ((_i) * 4))
 #define E1000_RSSIM    0x05864 /* RSS Interrupt Mask */
 #define E1000_RSSIR    0x05868 /* RSS Interrupt Request */
 /* VT Registers */
@@ -584,6 +596,14 @@
 #define E1000_SYNQF(_n)        (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
 #define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
 
+/* ETQF register bit definitions */
+#define E1000_ETQF_FILTER_ENABLE       (1 << 26)
+#define E1000_ETQF_IMM_INT             (1 << 29)
+#define E1000_ETQF_QUEUE_ENABLE                (1 << 31)
+#define E1000_ETQF_QUEUE_SHIFT         16
+#define E1000_ETQF_QUEUE_MASK          0x00070000
+#define E1000_ETQF_ETYPE_MASK          0x0000FFFF
+
 #define E1000_RTTDCS   0x3600 /* Reedtown Tx Desc plane control and status */
 #define E1000_RTTPCS   0x3474 /* Reedtown Tx Packet Plane control and status */
 #define E1000_RTRPCS   0x2474 /* Rx packet plane control and status */