for (i = 0; i < dev->data->nb_rx_queues; i++) {
eth_em_rx_queue_release(dev->data->rx_queues[i]);
dev->data->rx_queues[i] = NULL;
+ rte_eth_dma_zone_free(dev, "rx_ring", i);
}
dev->data->nb_rx_queues = 0;
for (i = 0; i < dev->data->nb_tx_queues; i++) {
eth_em_tx_queue_release(dev->data->tx_queues[i]);
dev->data->tx_queues[i] = NULL;
+ rte_eth_dma_zone_free(dev, "tx_ring", i);
}
dev->data->nb_tx_queues = 0;
}
tx_desc->lower.data = rte_cpu_to_le_32(txd_lower | size);
tx_desc->upper.data = 0;
- rte_wmb();
+ rte_cio_wmb();
txq->tx_tail++;
if (txq->tx_tail == txq->nb_tx_desc)
txq->tx_tail = 0;
- rte_io_wmb();
tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(i));
- E1000_PCI_REG_WRITE_RELAXED(tdt_reg_addr, txq->tx_tail);
+ E1000_PCI_REG_WRITE(tdt_reg_addr, txq->tx_tail);
usec_delay(250);
}
}
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
uint16_t pci_cfg_status = 0;
+ int ret;
fextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
E1000_WRITE_REG(hw, E1000_FEXTNVM11,
fextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);
tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
- rte_pci_read_config(pci_dev, &pci_cfg_status, sizeof(pci_cfg_status),
- PCI_CFG_STATUS_REG);
+ ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
+ sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
+ if (ret < 0) {
+ PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+ PCI_CFG_STATUS_REG);
+ return;
+ }
/* do nothing if we're not in faulty state, or if the queue is empty */
if ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {
/* flush desc ring */
e1000_flush_tx_ring(dev);
- rte_pci_read_config(pci_dev, &pci_cfg_status,
+ ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
+ if (ret < 0) {
+ PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+ PCI_CFG_STATUS_REG);
+ return;
+ }
+
if (pci_cfg_status & FLUSH_DESC_REQUIRED)
e1000_flush_rx_ring(dev);
}