net/qede: remove flags from Tx entry

[dpdk.git] / drivers / net / ena / base / ena_eth_com.c

diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c
index b6821a7..5583a31 100644 (file)
--- a/drivers/net/ena/base/ena_eth_com.c
+++ b/drivers/net/ena/base/ena_eth_com.c
@@ -278,7 +278,7 @@ static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
        meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
 
        /* bits 0-9 of the mss */
-       meta_desc->word2 |= (ena_meta->mss <<
+       meta_desc->word2 |= ((u32)ena_meta->mss <<
                ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) &
                ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
        /* bits 10-13 of the mss */
@@ -288,7 +288,7 @@ static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
 
        /* Extended meta desc */
        meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
-       meta_desc->len_ctrl |= (io_sq->phase <<
+       meta_desc->len_ctrl |= ((u32)io_sq->phase <<
                ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) &
                ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
 
@@ -301,7 +301,7 @@ static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
                ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) &
                ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
 
-       meta_desc->word2 |= (ena_meta->l4_hdr_len <<
+       meta_desc->word2 |= ((u32)ena_meta->l4_hdr_len <<
                ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) &
                ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
 
@@ -434,16 +434,16 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
        if (!have_meta)
                desc->len_ctrl |= ENA_ETH_IO_TX_DESC_FIRST_MASK;
 
-       desc->buff_addr_hi_hdr_sz |= (header_len <<
+       desc->buff_addr_hi_hdr_sz |= ((u32)header_len <<
                ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) &
                ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
-       desc->len_ctrl |= (io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
+       desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
                ENA_ETH_IO_TX_DESC_PHASE_MASK;
 
        desc->len_ctrl |= ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
 
        /* Bits 0-9 */
-       desc->meta_ctrl |= (ena_tx_ctx->req_id <<
+       desc->meta_ctrl |= ((u32)ena_tx_ctx->req_id <<
                ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) &
                ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
 
@@ -491,7 +491,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
 
                        memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
 
-                       desc->len_ctrl |= (io_sq->phase <<
+                       desc->len_ctrl |= ((u32)io_sq->phase <<
                                ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
                                ENA_ETH_IO_TX_DESC_PHASE_MASK;
                }
@@ -531,6 +531,7 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
 {
        struct ena_com_rx_buf_info *ena_buf = &ena_rx_ctx->ena_bufs[0];
        struct ena_eth_io_rx_cdesc_base *cdesc = NULL;
+       u16 q_depth = io_cq->q_depth;
        u16 cdesc_idx = 0;
        u16 nb_hw_desc;
        u16 i = 0;
@@ -557,10 +558,17 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
        ena_rx_ctx->pkt_offset = cdesc->offset;
 
        do {
-               ena_buf->len = cdesc->length;
-               ena_buf->req_id = cdesc->req_id;
-               ena_buf++;
-       } while ((++i < nb_hw_desc) && (cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i)));
+               ena_buf[i].len = cdesc->length;
+               ena_buf[i].req_id = cdesc->req_id;
+               if (unlikely(ena_buf[i].req_id >= q_depth))
+                       return ENA_COM_EIO;
+
+               if (++i >= nb_hw_desc)
+                       break;
+
+               cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i);
+
+       } while (1);
 
        /* Update SQ head ptr */
        io_sq->next_to_comp += nb_hw_desc;