#define DRV_MODULE_VER_MAJOR 2
#define DRV_MODULE_VER_MINOR 0
-#define DRV_MODULE_VER_SUBMINOR 1
+#define DRV_MODULE_VER_SUBMINOR 3
#define ENA_IO_TXQ_IDX(q) (2 * (q))
#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
packet_type |= RTE_PTYPE_L3_IPV6;
- if (unlikely(ena_rx_ctx->l4_csum_err))
- ol_flags |= PKT_RX_L4_CKSUM_BAD;
+ if (!ena_rx_ctx->l4_csum_checked)
+ ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
+ else
+ if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
+ ol_flags |= PKT_RX_L4_CKSUM_BAD;
+ else
+ ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
+
if (unlikely(ena_rx_ctx->l3_csum_err))
ol_flags |= PKT_RX_IP_CKSUM_BAD;
ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
host_info->num_cpus = rte_lcore_count();
+ host_info->driver_supported_features =
+ ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
+
rc = ena_com_set_host_attributes(ena_dev);
if (rc) {
if (rc == -ENA_COM_UNSUPPORTED)
if (ring->type == ENA_RING_TYPE_TX) {
ring->tx_stats.available_desc =
- ena_com_free_desc(ring->ena_com_io_sq);
+ ena_com_free_q_entries(ring->ena_com_io_sq);
return 0;
}
ena_rx_ctx.max_bufs = rx_ring->sgl_size;
ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
ena_rx_ctx.descs = 0;
+ ena_rx_ctx.pkt_offset = 0;
/* receive packet context */
rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
rx_ring->ena_com_io_sq,
mbuf->nb_segs = ena_rx_ctx.descs;
mbuf->port = rx_ring->port_id;
mbuf->pkt_len = 0;
+ mbuf->data_off += ena_rx_ctx.pkt_offset;
mbuf_head = mbuf;
} else {
/* for multi-segment pkts create mbuf chain */
tx_ring->tx_stats.bytes += total_length;
}
tx_ring->tx_stats.available_desc =
- ena_com_free_desc(tx_ring->ena_com_io_sq);
+ ena_com_free_q_entries(tx_ring->ena_com_io_sq);
/* If there are ready packets to be xmitted... */
if (sent_idx > 0) {
break;
}
tx_ring->tx_stats.available_desc =
- ena_com_free_desc(tx_ring->ena_com_io_sq);
+ ena_com_free_q_entries(tx_ring->ena_com_io_sq);
if (total_tx_descs > 0) {
/* acknowledge completion of sent packets */