#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-#define ENA_MAX_RING_DESC ENA_DEFAULT_RING_SIZE
#define ENA_MIN_RING_DESC 128
enum ethtool_stringset {
#define ENA_STAT_GLOBAL_ENTRY(stat) \
ENA_STAT_ENTRY(stat, dev)
+#define ENA_MAX_RING_SIZE_RX 8192
+#define ENA_MAX_RING_SIZE_TX 1024
+
/*
* Each rte_memzone should have unique name.
* To satisfy it, count number of allocation and add it to name.
#define ENA_TX_OFFLOAD_MASK (\
PKT_TX_L4_MASK | \
+ PKT_TX_IPV6 | \
+ PKT_TX_IPV4 | \
PKT_TX_IP_CKSUM | \
PKT_TX_TCP_SEG)
static int ena_link_update(struct rte_eth_dev *dev,
int wait_to_complete);
static int ena_create_io_queue(struct ena_ring *ring);
-static void ena_free_io_queues_all(struct ena_adapter *adapter);
-static int ena_queue_restart(struct ena_ring *ring);
-static int ena_queue_restart_all(struct rte_eth_dev *dev,
- enum ena_ring_type ring_type);
+static void ena_queue_stop(struct ena_ring *ring);
+static void ena_queue_stop_all(struct rte_eth_dev *dev,
+ enum ena_ring_type ring_type);
+static int ena_queue_start(struct ena_ring *ring);
+static int ena_queue_start_all(struct rte_eth_dev *dev,
+ enum ena_ring_type ring_type);
static void ena_stats_restart(struct rte_eth_dev *dev);
static void ena_infos_get(struct rte_eth_dev *dev,
struct rte_eth_dev_info *dev_info);
(DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
(DRV_MODULE_VER_SUBMINOR <<
ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
+ host_info->num_cpus = rte_lcore_count();
rc = ena_com_set_host_attributes(ena_dev);
if (rc) {
ena_com_admin_aenq_enable(ena_dev);
for (i = 0; i < nb_queues; ++i)
- ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
- mb_pool_rx[i]);
+ ena_rx_queue_setup(eth_dev, i, adapter->rx_ring[i].ring_size, 0,
+ NULL, mb_pool_rx[i]);
for (i = 0; i < nb_queues; ++i)
- ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
+ ena_tx_queue_setup(eth_dev, i, adapter->tx_ring[i].ring_size, 0,
+ NULL);
adapter->trigger_reset = false;
rte_free(ring->rx_buffer_info);
ring->rx_buffer_info = NULL;
+ if (ring->rx_refill_buffer)
+ rte_free(ring->rx_refill_buffer);
+ ring->rx_refill_buffer = NULL;
+
if (ring->empty_rx_reqs)
rte_free(ring->empty_rx_reqs);
ring->empty_rx_reqs = NULL;
ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
"API violation");
- /* Free all bufs */
- ena_tx_queue_release_bufs(ring);
-
/* Free ring resources */
+ if (ring->push_buf_intermediate_buf)
+ rte_free(ring->push_buf_intermediate_buf);
+
if (ring->tx_buffer_info)
rte_free(ring->tx_buffer_info);
ring->empty_tx_reqs = NULL;
ring->tx_buffer_info = NULL;
+ ring->push_buf_intermediate_buf = NULL;
ring->configured = 0;
return 0;
}
-static int ena_queue_restart_all(struct rte_eth_dev *dev,
- enum ena_ring_type ring_type)
+static int ena_queue_start_all(struct rte_eth_dev *dev,
+ enum ena_ring_type ring_type)
{
struct ena_adapter *adapter =
(struct ena_adapter *)(dev->data->dev_private);
"Inconsistent state of tx queues\n");
}
- rc = ena_queue_restart(&queues[i]);
+ rc = ena_queue_start(&queues[i]);
if (rc) {
PMD_INIT_LOG(ERR,
- "failed to restart queue %d type(%d)",
+ "failed to start queue %d type(%d)",
i, ring_type);
- return rc;
+ goto err;
}
}
}
return 0;
+
+err:
+ while (i--)
+ if (queues[i].configured)
+ ena_queue_stop(&queues[i]);
+
+ return rc;
}
static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
}
static int
-ena_calc_queue_size(struct ena_com_dev *ena_dev,
- u16 *max_tx_sgl_size,
- struct ena_com_dev_get_features_ctx *get_feat_ctx)
+ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
{
- uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
+ struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
+ struct ena_com_dev *ena_dev = ctx->ena_dev;
+ uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
+ uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
+
+ if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
+ struct ena_admin_queue_ext_feature_fields *max_queue_ext =
+ &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
+ rx_queue_size = RTE_MIN(rx_queue_size,
+ max_queue_ext->max_rx_cq_depth);
+ rx_queue_size = RTE_MIN(rx_queue_size,
+ max_queue_ext->max_rx_sq_depth);
+ tx_queue_size = RTE_MIN(tx_queue_size,
+ max_queue_ext->max_tx_cq_depth);
+
+ if (ena_dev->tx_mem_queue_type ==
+ ENA_ADMIN_PLACEMENT_POLICY_DEV) {
+ tx_queue_size = RTE_MIN(tx_queue_size,
+ llq->max_llq_depth);
+ } else {
+ tx_queue_size = RTE_MIN(tx_queue_size,
+ max_queue_ext->max_tx_sq_depth);
+ }
- queue_size = RTE_MIN(queue_size,
- get_feat_ctx->max_queues.max_cq_depth);
- queue_size = RTE_MIN(queue_size,
- get_feat_ctx->max_queues.max_sq_depth);
+ ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
+ max_queue_ext->max_per_packet_rx_descs);
+ ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
+ max_queue_ext->max_per_packet_tx_descs);
+ } else {
+ struct ena_admin_queue_feature_desc *max_queues =
+ &ctx->get_feat_ctx->max_queues;
+ rx_queue_size = RTE_MIN(rx_queue_size,
+ max_queues->max_cq_depth);
+ rx_queue_size = RTE_MIN(rx_queue_size,
+ max_queues->max_sq_depth);
+ tx_queue_size = RTE_MIN(tx_queue_size,
+ max_queues->max_cq_depth);
+
+ if (ena_dev->tx_mem_queue_type ==
+ ENA_ADMIN_PLACEMENT_POLICY_DEV) {
+ tx_queue_size = RTE_MIN(tx_queue_size,
+ llq->max_llq_depth);
+ } else {
+ tx_queue_size = RTE_MIN(tx_queue_size,
+ max_queues->max_sq_depth);
+ }
- if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
- queue_size = RTE_MIN(queue_size,
- get_feat_ctx->max_queues.max_llq_depth);
+ ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
+ max_queues->max_packet_tx_descs);
+ ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
+ max_queues->max_packet_rx_descs);
+ }
- /* Round down to power of 2 */
- if (!rte_is_power_of_2(queue_size))
- queue_size = rte_align32pow2(queue_size >> 1);
+ /* Round down to the nearest power of 2 */
+ rx_queue_size = rte_align32prevpow2(rx_queue_size);
+ tx_queue_size = rte_align32prevpow2(tx_queue_size);
- if (unlikely(queue_size == 0)) {
+ if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
PMD_INIT_LOG(ERR, "Invalid queue size");
return -EFAULT;
}
- *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
- get_feat_ctx->max_queues.max_packet_tx_descs);
+ ctx->rx_queue_size = rx_queue_size;
+ ctx->tx_queue_size = tx_queue_size;
- return queue_size;
+ return 0;
}
static void ena_stats_restart(struct rte_eth_dev *dev)
if (rc)
return rc;
- rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
+ rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
if (rc)
return rc;
- rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
+ rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
if (rc)
- return rc;
+ goto err_start_tx;
if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
rc = ena_rss_init_default(adapter);
if (rc)
- return rc;
+ goto err_rss_init;
}
ena_stats_restart(dev);
adapter->state = ENA_ADAPTER_STATE_RUNNING;
return 0;
+
+err_rss_init:
+ ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
+err_start_tx:
+ ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
+ return rc;
}
static void ena_stop(struct rte_eth_dev *dev)
(struct ena_adapter *)(dev->data->dev_private);
rte_timer_stop_sync(&adapter->timer_wd);
- ena_free_io_queues_all(adapter);
+ ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
+ ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
adapter->state = ENA_ADAPTER_STATE_STOPPED;
}
{ ENA_ADMIN_PLACEMENT_POLICY_HOST,
0, 0, 0, 0, 0 };
uint16_t ena_qid;
+ unsigned int i;
int rc;
adapter = ring->adapter;
ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
ctx.queue_size = adapter->tx_ring_size;
+ for (i = 0; i < ring->ring_size; i++)
+ ring->empty_tx_reqs[i] = i;
} else {
ena_qid = ENA_IO_RXQ_IDX(ring->id);
ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
ctx.queue_size = adapter->rx_ring_size;
+ for (i = 0; i < ring->ring_size; i++)
+ ring->empty_rx_reqs[i] = i;
}
ctx.qid = ena_qid;
ctx.msix_vector = -1; /* interrupts not used */
return 0;
}
-static void ena_free_io_queues_all(struct ena_adapter *adapter)
+static void ena_queue_stop(struct ena_ring *ring)
{
- struct rte_eth_dev *eth_dev = adapter->rte_dev;
- struct ena_com_dev *ena_dev = &adapter->ena_dev;
- int i;
- uint16_t ena_qid;
- uint16_t nb_rxq = eth_dev->data->nb_rx_queues;
- uint16_t nb_txq = eth_dev->data->nb_tx_queues;
+ struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
- for (i = 0; i < nb_txq; ++i) {
- ena_qid = ENA_IO_TXQ_IDX(i);
- ena_com_destroy_io_queue(ena_dev, ena_qid);
+ if (ring->type == ENA_RING_TYPE_RX) {
+ ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
+ ena_rx_queue_release_bufs(ring);
+ } else {
+ ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
+ ena_tx_queue_release_bufs(ring);
}
+}
- for (i = 0; i < nb_rxq; ++i) {
- ena_qid = ENA_IO_RXQ_IDX(i);
- ena_com_destroy_io_queue(ena_dev, ena_qid);
+static void ena_queue_stop_all(struct rte_eth_dev *dev,
+ enum ena_ring_type ring_type)
+{
+ struct ena_adapter *adapter =
+ (struct ena_adapter *)(dev->data->dev_private);
+ struct ena_ring *queues = NULL;
+ uint16_t nb_queues, i;
- ena_rx_queue_release_bufs(&adapter->rx_ring[i]);
+ if (ring_type == ENA_RING_TYPE_RX) {
+ queues = adapter->rx_ring;
+ nb_queues = dev->data->nb_rx_queues;
+ } else {
+ queues = adapter->tx_ring;
+ nb_queues = dev->data->nb_tx_queues;
}
+
+ for (i = 0; i < nb_queues; ++i)
+ if (queues[i].configured)
+ ena_queue_stop(&queues[i]);
}
-static int ena_queue_restart(struct ena_ring *ring)
+static int ena_queue_start(struct ena_ring *ring)
{
int rc, bufs_num;
ena_assert_msg(ring->configured == 1,
- "Trying to restart unconfigured queue\n");
+ "Trying to start unconfigured queue\n");
rc = ena_create_io_queue(ring);
if (rc) {
bufs_num = ring->ring_size - 1;
rc = ena_populate_rx_queue(ring, bufs_num);
if (rc != bufs_num) {
+ ena_com_destroy_io_queue(&ring->adapter->ena_dev,
+ ENA_IO_RXQ_IDX(ring->id));
PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
return ENA_COM_FAULT;
}
return -EINVAL;
}
+ if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
+ nb_desc = adapter->tx_ring_size;
+
txq->port_id = dev->data->port_id;
txq->next_to_clean = 0;
txq->next_to_use = 0;
return -ENOMEM;
}
+ txq->push_buf_intermediate_buf =
+ rte_zmalloc("txq->push_buf_intermediate_buf",
+ txq->tx_max_header_size,
+ RTE_CACHE_LINE_SIZE);
+ if (!txq->push_buf_intermediate_buf) {
+ RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n");
+ rte_free(txq->tx_buffer_info);
+ rte_free(txq->empty_tx_reqs);
+ return -ENOMEM;
+ }
+
for (i = 0; i < txq->ring_size; i++)
txq->empty_tx_reqs[i] = i;
return ENA_COM_FAULT;
}
+ if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
+ nb_desc = adapter->rx_ring_size;
+
if (!rte_is_power_of_2(nb_desc)) {
RTE_LOG(ERR, PMD,
"Unsupported size of RX queue: %d is not a power of 2.",
return -ENOMEM;
}
+ rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
+ sizeof(struct rte_mbuf *) * nb_desc,
+ RTE_CACHE_LINE_SIZE);
+
+ if (!rxq->rx_refill_buffer) {
+ RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
+ rte_free(rxq->rx_buffer_info);
+ rxq->rx_buffer_info = NULL;
+ return -ENOMEM;
+ }
+
rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
sizeof(uint16_t) * nb_desc,
RTE_CACHE_LINE_SIZE);
RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
rte_free(rxq->rx_buffer_info);
rxq->rx_buffer_info = NULL;
+ rte_free(rxq->rx_refill_buffer);
+ rxq->rx_refill_buffer = NULL;
return -ENOMEM;
}
uint16_t ring_mask = ring_size - 1;
uint16_t next_to_use = rxq->next_to_use;
uint16_t in_use, req_id;
- struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
+ struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
if (unlikely(!count))
return 0;
in_use = rxq->next_to_use - rxq->next_to_clean;
ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
- count = RTE_MIN(count,
- (uint16_t)(ring_size - (next_to_use & ring_mask)));
-
/* get resources for incoming packets */
- rc = rte_mempool_get_bulk(rxq->mb_pool,
- (void **)(&mbufs[next_to_use & ring_mask]),
- count);
+ rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
if (unlikely(rc < 0)) {
rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
PMD_RX_LOG(DEBUG, "there are no enough free buffers");
for (i = 0; i < count; i++) {
uint16_t next_to_use_masked = next_to_use & ring_mask;
- struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
+ struct rte_mbuf *mbuf = mbufs[i];
struct ena_com_buf ebuf;
- rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
+ if (likely((i + 4) < count))
+ rte_prefetch0(mbufs[i + 4]);
req_id = rxq->empty_rx_reqs[next_to_use_masked];
rc = validate_rx_req_id(rxq, req_id);
if (unlikely(rc < 0))
break;
+ rxq->rx_buffer_info[req_id] = mbuf;
/* prepare physical address for DMA transaction */
ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
&ebuf, req_id);
if (unlikely(rc)) {
- rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
- count - i);
RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
+ rxq->rx_buffer_info[req_id] = NULL;
break;
}
next_to_use++;
}
- if (unlikely(i < count))
+ if (unlikely(i < count)) {
RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
"buffers (from %d)\n", rxq->id, i, count);
+ rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
+ count - i);
+ }
/* When we submitted free recources to device... */
if (likely(i > 0)) {
ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
/* ENA device administration layer init */
- rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
+ rc = ena_com_admin_init(ena_dev, &aenq_handlers);
if (rc) {
RTE_LOG(ERR, PMD,
"cannot initialize ena admin queue with device\n");
}
}
-static int ena_calc_io_queue_num(__rte_unused struct ena_com_dev *ena_dev,
+static inline void
+set_default_llq_configurations(struct ena_llq_configurations *llq_config)
+{
+ llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
+ llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
+ llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
+ llq_config->llq_num_decs_before_header =
+ ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
+ llq_config->llq_ring_entry_size_value = 128;
+}
+
+static int
+ena_set_queues_placement_policy(struct ena_adapter *adapter,
+ struct ena_com_dev *ena_dev,
+ struct ena_admin_feature_llq_desc *llq,
+ struct ena_llq_configurations *llq_default_configurations)
+{
+ int rc;
+ u32 llq_feature_mask;
+
+ llq_feature_mask = 1 << ENA_ADMIN_LLQ;
+ if (!(ena_dev->supported_features & llq_feature_mask)) {
+ RTE_LOG(INFO, PMD,
+ "LLQ is not supported. Fallback to host mode policy.\n");
+ ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
+ return 0;
+ }
+
+ rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
+ if (unlikely(rc)) {
+ PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
+ "Fallback to host mode policy.\n");
+ ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
+ return 0;
+ }
+
+ /* Nothing to config, exit */
+ if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
+ return 0;
+
+ if (!adapter->dev_mem_base) {
+ RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. "
+ "Fallback to host mode policy.\n.");
+ ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
+ return 0;
+ }
+
+ ena_dev->mem_bar = adapter->dev_mem_base;
+
+ return 0;
+}
+
+static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
struct ena_com_dev_get_features_ctx *get_feat_ctx)
{
- int io_sq_num, io_cq_num, io_queue_num;
+ uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
+
+ /* Regular queues capabilities */
+ if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
+ struct ena_admin_queue_ext_feature_fields *max_queue_ext =
+ &get_feat_ctx->max_queue_ext.max_queue_ext;
+ io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
+ max_queue_ext->max_rx_cq_num);
+ io_tx_sq_num = max_queue_ext->max_tx_sq_num;
+ io_tx_cq_num = max_queue_ext->max_tx_cq_num;
+ } else {
+ struct ena_admin_queue_feature_desc *max_queues =
+ &get_feat_ctx->max_queues;
+ io_tx_sq_num = max_queues->max_sq_num;
+ io_tx_cq_num = max_queues->max_cq_num;
+ io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
+ }
- io_sq_num = get_feat_ctx->max_queues.max_sq_num;
- io_cq_num = get_feat_ctx->max_queues.max_cq_num;
+ /* In case of LLQ use the llq number in the get feature cmd */
+ if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
+ io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
- io_queue_num = RTE_MIN(io_sq_num, io_cq_num);
+ io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES);
+ io_queue_num = RTE_MIN(io_queue_num, io_rx_num);
+ io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
+ io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
if (unlikely(io_queue_num == 0)) {
RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
{
+ struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
struct rte_pci_device *pci_dev;
struct rte_intr_handle *intr_handle;
struct ena_adapter *adapter =
(struct ena_adapter *)(eth_dev->data->dev_private);
struct ena_com_dev *ena_dev = &adapter->ena_dev;
struct ena_com_dev_get_features_ctx get_feat_ctx;
- int queue_size, rc;
- u16 tx_sgl_size = 0;
+ struct ena_llq_configurations llq_config;
+ const char *queue_type_str;
+ int rc;
static int adapters_found;
bool wd_state;
}
adapter->wd_state = wd_state;
- ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
+ set_default_llq_configurations(&llq_config);
+ rc = ena_set_queues_placement_policy(adapter, ena_dev,
+ &get_feat_ctx.llq, &llq_config);
+ if (unlikely(rc)) {
+ PMD_INIT_LOG(CRIT, "Failed to set placement policy");
+ return rc;
+ }
+
+ if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
+ queue_type_str = "Regular";
+ else
+ queue_type_str = "Low latency";
+ RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str);
+
+ calc_queue_ctx.ena_dev = ena_dev;
+ calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
adapter->num_queues = ena_calc_io_queue_num(ena_dev,
&get_feat_ctx);
- queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx);
- if (queue_size <= 0 || adapter->num_queues <= 0) {
+ rc = ena_calc_queue_size(&calc_queue_ctx);
+ if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
rc = -EFAULT;
goto err_device_destroy;
}
- adapter->tx_ring_size = queue_size;
- adapter->rx_ring_size = queue_size;
+ adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
+ adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
- adapter->max_tx_sgl_size = tx_sgl_size;
+ adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
+ adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
/* prepare ring structures */
ena_init_rings(adapter);
ring->type = ENA_RING_TYPE_RX;
ring->adapter = adapter;
ring->id = i;
+ ring->sgl_size = adapter->max_rx_sgl_size;
}
}
adapter->tx_supported_offloads = tx_feat;
adapter->rx_supported_offloads = rx_feat;
- dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC;
+ dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
+ dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
+ adapter->max_rx_sgl_size);
+ dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
+ adapter->max_rx_sgl_size);
- dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC;
+ dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
- feat.max_queues.max_packet_tx_descs);
+ adapter->max_tx_sgl_size);
dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
- feat.max_queues.max_packet_tx_descs);
+ adapter->max_tx_sgl_size);
}
static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
for (completed = 0; completed < nb_pkts; completed++) {
int segments = 0;
- ena_rx_ctx.max_bufs = rx_ring->ring_size;
+ ena_rx_ctx.max_bufs = rx_ring->sgl_size;
ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
ena_rx_ctx.descs = 0;
/* receive packet context */
&ena_rx_ctx);
if (unlikely(rc)) {
RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
+ rx_ring->adapter->reset_reason =
+ ENA_REGS_RESET_TOO_MANY_RX_DESCS;
rx_ring->adapter->trigger_reset = true;
return 0;
}
segments++;
next_to_clean++;
}
+ if (unlikely(rc))
+ break;
/* fill mbuf attributes if any */
ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
struct rte_mbuf *mbuf)
{
- int num_segments, rc;
+ struct ena_com_dev *ena_dev;
+ int num_segments, header_len, rc;
+ ena_dev = &tx_ring->adapter->ena_dev;
num_segments = mbuf->nb_segs;
+ header_len = mbuf->data_len;
if (likely(num_segments < tx_ring->sgl_size))
return 0;
+ if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
+ (num_segments == tx_ring->sgl_size) &&
+ (header_len < tx_ring->tx_max_header_size))
+ return 0;
+
rc = rte_pktmbuf_linearize(mbuf);
if (unlikely(rc))
RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
uint16_t next_to_use = tx_ring->next_to_use;
uint16_t next_to_clean = tx_ring->next_to_clean;
struct rte_mbuf *mbuf;
+ uint16_t seg_len;
unsigned int ring_size = tx_ring->ring_size;
unsigned int ring_mask = ring_size - 1;
struct ena_com_tx_ctx ena_tx_ctx;
struct ena_com_buf *ebuf;
uint16_t rc, req_id, total_tx_descs = 0;
uint16_t sent_idx = 0, empty_tx_reqs;
+ uint16_t push_len = 0;
+ uint16_t delta = 0;
int nb_hw_desc;
/* Check adapter state */
sizeof(struct ena_com_tx_meta));
ena_tx_ctx.ena_bufs = ebuf;
ena_tx_ctx.req_id = req_id;
+
+ delta = 0;
+ seg_len = mbuf->data_len;
+
if (tx_ring->tx_mem_queue_type ==
ENA_ADMIN_PLACEMENT_POLICY_DEV) {
- /* prepare the push buffer with
- * virtual address of the data
- */
- ena_tx_ctx.header_len =
- RTE_MIN(mbuf->data_len,
- tx_ring->tx_max_header_size);
- ena_tx_ctx.push_header =
- (void *)((char *)mbuf->buf_addr +
- mbuf->data_off);
+ push_len = RTE_MIN(mbuf->pkt_len,
+ tx_ring->tx_max_header_size);
+ ena_tx_ctx.header_len = push_len;
+
+ if (likely(push_len <= seg_len)) {
+ /* If the push header is in the single segment,
+ * then just point it to the 1st mbuf data.
+ */
+ ena_tx_ctx.push_header =
+ rte_pktmbuf_mtod(mbuf, uint8_t *);
+ } else {
+ /* If the push header lays in the several
+ * segments, copy it to the intermediate buffer.
+ */
+ rte_pktmbuf_read(mbuf, 0, push_len,
+ tx_ring->push_buf_intermediate_buf);
+ ena_tx_ctx.push_header =
+ tx_ring->push_buf_intermediate_buf;
+ delta = push_len - seg_len;
+ }
} /* there's no else as we take advantage of memset zeroing */
/* Set TX offloads flags, if applicable */
/* Process first segment taking into
* consideration pushed header
*/
- if (mbuf->data_len > ena_tx_ctx.header_len) {
+ if (seg_len > push_len) {
ebuf->paddr = mbuf->buf_iova +
mbuf->data_off +
- ena_tx_ctx.header_len;
- ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
+ push_len;
+ ebuf->len = seg_len - push_len;
ebuf++;
tx_info->num_of_bufs++;
}
while ((mbuf = mbuf->next) != NULL) {
- ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
- ebuf->len = mbuf->data_len;
+ seg_len = mbuf->data_len;
+
+ /* Skip mbufs if whole data is pushed as a header */
+ if (unlikely(delta > seg_len)) {
+ delta -= seg_len;
+ continue;
+ }
+
+ ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
+ ebuf->len = seg_len - delta;
ebuf++;
tx_info->num_of_bufs++;
+
+ delta = 0;
}
ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
- /* Write data to device */
+ if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
+ &ena_tx_ctx)) {
+ RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d"
+ " achieved, writing doorbell to send burst\n",
+ tx_ring->id);
+ rte_wmb();
+ ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
+ }
+
+ /* prepare the packet's descriptors to dma engine */
rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
&ena_tx_ctx, &nb_hw_desc);
if (unlikely(rc))
git.droids-corp.org / dpdk.git / blobdiff