#define _ENA_ETHDEV_H_
#include <rte_pci.h>
+#include <rte_bus_pci.h>
#include "ena_com.h"
#define ENA_MEM_BAR 2
#define ENA_MAX_NUM_QUEUES 128
-
-#define ENA_DEFAULT_TX_SW_DESCS (1024)
-#define ENA_DEFAULT_TX_HW_DESCS (1024)
#define ENA_DEFAULT_RING_SIZE (1024)
-
#define ENA_MIN_FRAME_LEN 64
-
-#define ENA_NAME_MAX_LEN 20
-#define ENA_IRQNAME_SIZE 40
-
-#define ENA_PKT_MAX_BUFS 17
+#define ENA_NAME_MAX_LEN 20
+#define ENA_PKT_MAX_BUFS 17
#define ENA_MMIO_DISABLE_REG_READ BIT(0)
-#define ENA_CIRC_COUNT(head, tail, size) \
- (((uint16_t)((uint16_t)(head) - (uint16_t)(tail))) & ((size) - 1))
-
-#define ENA_CIRC_INC(index, step, size) \
- ((uint16_t)(index) + (uint16_t)(step))
-#define ENA_CIRC_INC_WRAP(index, step, size) \
- (((uint16_t)(index) + (uint16_t)(step)) & ((size) - 1))
-
-#define ENA_TX_RING_IDX_NEXT(idx, ring_size) \
- ENA_CIRC_INC_WRAP(idx, 1, ring_size)
-#define ENA_RX_RING_IDX_NEXT(idx, ring_size) \
- ENA_CIRC_INC_WRAP(idx, 1, ring_size)
-
struct ena_adapter;
enum ena_ring_type {
uint8_t tx_max_header_size;
int configured;
struct ena_adapter *adapter;
+ uint64_t offloads;
} __rte_cache_aligned;
enum ena_adapter_state {
u16 num_queues;
u16 max_mtu;
+ u8 tso4_supported;
int id_number;
char name[ENA_NAME_MAX_LEN];
struct ena_driver_stats *drv_stats;
enum ena_adapter_state state;
+ uint64_t tx_supported_offloads;
+ uint64_t tx_selected_offloads;
+ uint64_t rx_supported_offloads;
+ uint64_t rx_selected_offloads;
};
#endif /* _ENA_ETHDEV_H_ */