#define ENA_RX_BUF_MIN_SIZE 1400
#define ENA_DEFAULT_RING_SIZE 1024
+#define ENA_RX_RSS_TABLE_LOG_SIZE 7
+#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
+
#define ENA_MIN_MTU 128
#define ENA_MMIO_DISABLE_REG_READ BIT(0)
#define ENA_WD_TIMEOUT_SEC 3
#define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
+#define ENA_TX_TIMEOUT (5 * rte_get_timer_hz())
+#define ENA_MAX_TX_TIMEOUT_SECONDS 60
+#define ENA_MONITORED_TX_QUEUES 3
+#define ENA_DEFAULT_MISSING_COMP 256U
+
/* While processing submitted and completed descriptors (rx and tx path
* respectively) in a loop it is desired to:
- * - perform batch submissions while populating sumbissmion queue
+ * - perform batch submissions while populating submission queue
* - avoid blocking transmission of other packets during cleanup phase
* Hence the utilization ratio of 1/8 of a queue size or max value if the size
* of the ring is very big - like 8k Rx rings.
#define ENA_HASH_KEY_SIZE 40
-#define ENA_ALL_RSS_HF (ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
- ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_UDP)
+#define ENA_ALL_RSS_HF (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
+ RTE_ETH_RSS_NONFRAG_IPV6_TCP | RTE_ETH_RSS_NONFRAG_IPV6_UDP)
#define ENA_IO_TXQ_IDX(q) (2 * (q))
#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
struct rte_mbuf *mbuf;
unsigned int tx_descs;
unsigned int num_of_bufs;
+ uint64_t timestamp;
+ bool print_once;
struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
};
u64 cnt;
u64 bytes;
u64 prepare_ctx_err;
- u64 linearize;
- u64 linearize_failed;
u64 tx_poll;
u64 doorbells;
u64 bad_req_id;
u64 available_desc;
+ u64 missed_tx;
};
struct ena_stats_rx {
u64 cnt;
u64 bytes;
u64 refill_partial;
- u64 bad_csum;
+ u64 l3_csum_bad;
+ u64 l4_csum_bad;
+ u64 l4_csum_good;
u64 mbuf_alloc_fail;
u64 bad_desc_num;
u64 bad_req_id;
struct ena_ring {
u16 next_to_use;
u16 next_to_clean;
+ uint64_t last_cleanup_ticks;
enum ena_ring_type type;
enum ena_admin_placement_policy_type tx_mem_queue_type;
struct ena_com_io_cq *ena_com_io_cq;
struct ena_com_io_sq *ena_com_io_sq;
+ union {
+ uint16_t tx_free_thresh;
+ uint16_t rx_free_thresh;
+ };
+
struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
__rte_cache_aligned;
};
unsigned int numa_socket_id;
+
+ uint32_t missing_tx_completion_threshold;
} __rte_cache_aligned;
enum ena_adapter_state {
};
struct ena_offloads {
- bool tso4_supported;
- bool tx_csum_supported;
- bool rx_csum_supported;
- bool rss_hash_supported;
+ uint32_t tx_offloads;
+ uint32_t rx_offloads;
};
/* board specific private data structure */
struct ena_driver_stats *drv_stats;
enum ena_adapter_state state;
- uint64_t tx_supported_offloads;
- uint64_t tx_selected_offloads;
- uint64_t rx_supported_offloads;
- uint64_t rx_selected_offloads;
-
bool link_status;
enum ena_regs_reset_reason_types reset_reason;
struct ena_stats_dev dev_stats;
struct ena_stats_eni eni_stats;
+ struct ena_admin_basic_stats basic_stats;
- bool trigger_reset;
+ u32 indirect_table[ENA_RX_RSS_TABLE_SIZE];
- bool wd_state;
+ uint32_t all_aenq_groups;
+ uint32_t active_aenq_groups;
+
+ bool trigger_reset;
bool use_large_llq_hdr;
+
+ uint32_t last_tx_comp_qid;
+ uint64_t missing_tx_completion_to;
+ uint64_t missing_tx_completion_budget;
+ uint64_t tx_cleanup_stall_delay;
+
+ uint64_t memzone_cnt;
};
+int ena_mp_indirect_table_set(struct ena_adapter *adapter);
+int ena_mp_indirect_table_get(struct ena_adapter *adapter,
+ uint32_t *indirect_table);
int ena_rss_reta_update(struct rte_eth_dev *dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size);