/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright 2018 NXP
+ * Copyright 2018-2019 NXP
*/
#ifndef _ENETC_H_
/* Max RX rings per ENTEC. */
#define MAX_RX_RINGS 1
+/* Max BD counts per Ring. */
+#define MAX_BD_COUNT 64000
+/* Min BD counts per Ring. */
+#define MIN_BD_COUNT 32
+/* BD ALIGN */
+#define BD_ALIGN 8
+
+/* minimum frame size supported */
+#define ENETC_MAC_MINFRM_SIZE 68
+/* maximum frame size supported */
+#define ENETC_MAC_MAXFRM_SIZE 9600
+
/*
* upper_32_bits - return bits 32-63 of a number
* @n: the number we're accessing
};
struct enetc_bdr {
- struct rte_eth_dev *ndev;
- struct rte_mempool *mb_pool; /* mbuf pool to populate RX ring. */
void *bd_base; /* points to Rx or Tx BD ring */
+ struct enetc_swbd *q_swbd;
union {
void *tcir;
void *rcir;
};
- uint16_t index;
int bd_count; /* # of BDs */
int next_to_use;
int next_to_clean;
- struct enetc_swbd *q_swbd;
+ uint16_t index;
+ uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
union {
void *tcisr; /* Tx */
int next_to_alloc; /* Rx */
};
+ struct rte_mempool *mb_pool; /* mbuf pool to populate RX ring. */
+ struct rte_eth_dev *ndev;
};
/*
#define ENETC_DEV_PRIVATE_TO_INTR(adapter) \
(&((struct enetc_eth_adapter *)adapter)->intr)
-#define ENETC_GET_HW_ADDR(reg, addr) ((void *)(((size_t)reg) + (addr)))
-#define ENETC_REG_READ(addr) (*(uint32_t *)addr)
-#define ENETC_REG_WRITE(addr, val) (*(uint32_t *)addr = val)
-#define ENETC_REG_WRITE_RELAXED(addr, val) (*(uint32_t *)addr = val)
+/*
+ * RX/TX ENETC function prototypes
+ */
+uint16_t enetc_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
+uint16_t enetc_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts);
+
+
+int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt);
+
+static inline int
+enetc_bd_unused(struct enetc_bdr *bdr)
+{
+ if (bdr->next_to_clean > bdr->next_to_use)
+ return bdr->next_to_clean - bdr->next_to_use - 1;
+ return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1;
+}
#endif /* _ENETC_H_ */