*/
#include <stdbool.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_pci.h>
#include <rte_random.h>
#include <dpaax_iova_table.h>
return 0;
}
-static void
+static int
enetc_dev_stop(struct rte_eth_dev *dev)
{
struct enetc_eth_hw *hw =
uint32_t val;
PMD_INIT_FUNC_TRACE();
+ dev->data->dev_started = 0;
/* Disable port */
val = enetc_port_rd(enetc_hw, ENETC_PMR);
enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN));
val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN)));
+
+ return 0;
}
static const uint32_t *
enetc_dev_close(struct rte_eth_dev *dev)
{
uint16_t i;
+ int ret;
PMD_INIT_FUNC_TRACE();
- enetc_dev_stop(dev);
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
+ ret = enetc_dev_stop(dev);
for (i = 0; i < dev->data->nb_rx_queues; i++) {
enetc_rx_queue_release(dev->data->rx_queues[i]);
if (rte_eal_iova_mode() == RTE_IOVA_PA)
dpaax_iova_table_depopulate();
- return 0;
+ return ret;
}
static int
return -EINVAL;
}
- if (frame_size > RTE_ETHER_MAX_LEN)
+ if (frame_size > ENETC_ETH_MAX_LEN)
dev->data->dev_conf.rxmode.offloads &=
DEV_RX_OFFLOAD_JUMBO_FRAME;
else
eth_dev->dev_ops = &enetc_ops;
eth_dev->rx_pkt_burst = &enetc_recv_pkts;
eth_dev->tx_pkt_burst = &enetc_xmit_pkts;
- eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
+
+ eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
/* Retrieving and storing the HW base address of device */
hw->hw.reg = (void *)pci_dev->mem_resource[0].addr;