/* Completion queue control */
struct vnic_cq_ctrl {
- u64 ring_base; /* 0x00 */
- u32 ring_size; /* 0x08 */
- u32 pad0;
- u32 flow_control_enable; /* 0x10 */
- u32 pad1;
- u32 color_enable; /* 0x18 */
- u32 pad2;
- u32 cq_head; /* 0x20 */
- u32 pad3;
- u32 cq_tail; /* 0x28 */
- u32 pad4;
- u32 cq_tail_color; /* 0x30 */
- u32 pad5;
- u32 interrupt_enable; /* 0x38 */
- u32 pad6;
- u32 cq_entry_enable; /* 0x40 */
- u32 pad7;
- u32 cq_message_enable; /* 0x48 */
- u32 pad8;
- u32 interrupt_offset; /* 0x50 */
- u32 pad9;
- u64 cq_message_addr; /* 0x58 */
- u32 pad10;
+ uint64_t ring_base; /* 0x00 */
+ uint32_t ring_size; /* 0x08 */
+ uint32_t pad0;
+ uint32_t flow_control_enable; /* 0x10 */
+ uint32_t pad1;
+ uint32_t color_enable; /* 0x18 */
+ uint32_t pad2;
+ uint32_t cq_head; /* 0x20 */
+ uint32_t pad3;
+ uint32_t cq_tail; /* 0x28 */
+ uint32_t pad4;
+ uint32_t cq_tail_color; /* 0x30 */
+ uint32_t pad5;
+ uint32_t interrupt_enable; /* 0x38 */
+ uint32_t pad6;
+ uint32_t cq_entry_enable; /* 0x40 */
+ uint32_t pad7;
+ uint32_t cq_message_enable; /* 0x48 */
+ uint32_t pad8;
+ uint32_t interrupt_offset; /* 0x50 */
+ uint32_t pad9;
+ uint64_t cq_message_addr; /* 0x58 */
+ uint32_t pad10;
};
#ifdef ENIC_AIC
unsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,
unsigned int cq_tail_color, unsigned int interrupt_enable,
unsigned int cq_entry_enable, unsigned int message_enable,
- unsigned int interrupt_offset, u64 message_addr);
+ unsigned int interrupt_offset, uint64_t message_addr);
void vnic_cq_clean(struct vnic_cq *cq);
int vnic_cq_mem_size(struct vnic_cq *cq, unsigned int desc_count,
unsigned int desc_size);