regex/mlx5: support enqueue
[dpdk.git] / drivers / net / enic / base / vnic_rq.h
index 7d96b0f..cfe6501 100644 (file)
@@ -1,77 +1,49 @@
-/*
- * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
- *
- * Copyright (c) 2014, Cisco Systems, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
  */
 
 #ifndef _VNIC_RQ_H_
 #define _VNIC_RQ_H_
 
+#include <stdbool.h>
 
 #include "vnic_dev.h"
 #include "vnic_cq.h"
 
 /* Receive queue control */
 struct vnic_rq_ctrl {
-       u64 ring_base;                  /* 0x00 */
-       u32 ring_size;                  /* 0x08 */
-       u32 pad0;
-       u32 posted_index;               /* 0x10 */
-       u32 pad1;
-       u32 cq_index;                   /* 0x18 */
-       u32 pad2;
-       u32 enable;                     /* 0x20 */
-       u32 pad3;
-       u32 running;                    /* 0x28 */
-       u32 pad4;
-       u32 fetch_index;                /* 0x30 */
-       u32 pad5;
-       u32 error_interrupt_enable;     /* 0x38 */
-       u32 pad6;
-       u32 error_interrupt_offset;     /* 0x40 */
-       u32 pad7;
-       u32 error_status;               /* 0x48 */
-       u32 pad8;
-       u32 tcp_sn;                     /* 0x50 */
-       u32 pad9;
-       u32 unused;                     /* 0x58 */
-       u32 pad10;
-       u32 dca_select;                 /* 0x60 */
-       u32 pad11;
-       u32 dca_value;                  /* 0x68 */
-       u32 pad12;
-       u32 data_ring;                  /* 0x70 */
-       u32 pad13;
-       u32 header_split;               /* 0x78 */
-       u32 pad14;
+       uint64_t ring_base;                     /* 0x00 */
+       uint32_t ring_size;                     /* 0x08 */
+       uint32_t pad0;
+       uint32_t posted_index;                  /* 0x10 */
+       uint32_t pad1;
+       uint32_t cq_index;                      /* 0x18 */
+       uint32_t pad2;
+       uint32_t enable;                        /* 0x20 */
+       uint32_t pad3;
+       uint32_t running;                       /* 0x28 */
+       uint32_t pad4;
+       uint32_t fetch_index;                   /* 0x30 */
+       uint32_t pad5;
+       uint32_t error_interrupt_enable;        /* 0x38 */
+       uint32_t pad6;
+       uint32_t error_interrupt_offset;        /* 0x40 */
+       uint32_t pad7;
+       uint32_t error_status;                  /* 0x48 */
+       uint32_t pad8;
+       uint32_t tcp_sn;                        /* 0x50 */
+       uint32_t pad9;
+       uint32_t unused;                        /* 0x58 */
+       uint32_t pad10;
+       uint32_t dca_select;                    /* 0x60 */
+       uint32_t pad11;
+       uint32_t dca_value;                     /* 0x68 */
+       uint32_t pad12;
+       uint32_t data_ring;                     /* 0x70 */
+       uint32_t pad13;
+       uint32_t header_split;                  /* 0x78 */
+       uint32_t pad14;
 };
 
 struct vnic_rq {
@@ -80,6 +52,8 @@ struct vnic_rq {
        struct vnic_dev *vdev;
        struct vnic_rq_ctrl __iomem *ctrl;      /* memory-mapped */
        struct vnic_dev_ring ring;
+       struct rte_mbuf **free_mbufs;           /* reserve of free mbufs */
+       int num_free_mbufs;
        struct rte_mbuf **mbuf_ring;            /* array of allocated mbufs */
        unsigned int mbuf_next_idx;             /* next mb to consume */
        void *os_buf_head;
@@ -91,12 +65,14 @@ struct vnic_rq {
        uint16_t rxst_idx;
        uint32_t tot_pkts;
        uint16_t data_queue_idx;
+       uint8_t data_queue_enable;
        uint8_t is_sop;
        uint8_t in_use;
        struct rte_mbuf *pkt_first_seg;
        struct rte_mbuf *pkt_last_seg;
        unsigned int max_mbufs_per_pkt;
        uint16_t tot_nb_desc;
+       bool need_initial_post;
 };
 
 static inline unsigned int vnic_rq_desc_avail(struct vnic_rq *rq)