net/mlx5: share Rx queue indirection table code

[dpdk.git] / drivers / net / enic / base / vnic_wq.h

diff --git a/drivers/net/enic/base/vnic_wq.h b/drivers/net/enic/base/vnic_wq.h
index 7c069c0..789a50a 100644 (file)
--- a/drivers/net/enic/base/vnic_wq.h
+++ b/drivers/net/enic/base/vnic_wq.h
@@ -13,46 +13,43 @@
 
 /* Work queue control */
 struct vnic_wq_ctrl {
-       u64 ring_base;                  /* 0x00 */
-       u32 ring_size;                  /* 0x08 */
-       u32 pad0;
-       u32 posted_index;               /* 0x10 */
-       u32 pad1;
-       u32 cq_index;                   /* 0x18 */
-       u32 pad2;
-       u32 enable;                     /* 0x20 */
-       u32 pad3;
-       u32 running;                    /* 0x28 */
-       u32 pad4;
-       u32 fetch_index;                /* 0x30 */
-       u32 pad5;
-       u32 dca_value;                  /* 0x38 */
-       u32 pad6;
-       u32 error_interrupt_enable;     /* 0x40 */
-       u32 pad7;
-       u32 error_interrupt_offset;     /* 0x48 */
-       u32 pad8;
-       u32 error_status;               /* 0x50 */
-       u32 pad9;
-};
-
-/* 16 bytes */
-struct vnic_wq_buf {
-       struct rte_mempool *pool;
-       void *mb;
+       uint64_t ring_base;                     /* 0x00 */
+       uint32_t ring_size;                     /* 0x08 */
+       uint32_t pad0;
+       uint32_t posted_index;                  /* 0x10 */
+       uint32_t pad1;
+       uint32_t cq_index;                      /* 0x18 */
+       uint32_t pad2;
+       uint32_t enable;                        /* 0x20 */
+       uint32_t pad3;
+       uint32_t running;                       /* 0x28 */
+       uint32_t pad4;
+       uint32_t fetch_index;                   /* 0x30 */
+       uint32_t pad5;
+       uint32_t dca_value;                     /* 0x38 */
+       uint32_t pad6;
+       uint32_t error_interrupt_enable;        /* 0x40 */
+       uint32_t pad7;
+       uint32_t error_interrupt_offset;        /* 0x48 */
+       uint32_t pad8;
+       uint32_t error_status;                  /* 0x50 */
+       uint32_t pad9;
 };
 
 struct vnic_wq {
        unsigned int index;
+       uint64_t tx_offload_notsup_mask;
        struct vnic_dev *vdev;
        struct vnic_wq_ctrl __iomem *ctrl;              /* memory-mapped */
        struct vnic_dev_ring ring;
-       struct vnic_wq_buf *bufs;
+       struct rte_mbuf **bufs;
        unsigned int head_idx;
+       unsigned int cq_pend;
        unsigned int tail_idx;
        unsigned int socket_id;
        const struct rte_memzone *cqmsg_rz;
        uint16_t last_completed_index;
+       uint64_t offloads;
 };
 
 static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
@@ -122,7 +119,8 @@ static inline unsigned int num_cache_lines_touched(dma_addr_t addr,
        return lines >> PI_LOG2_CACHE_LINE_SIZE;
 }
 
-static inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,
+static inline uint64_t vnic_cached_posted_index(dma_addr_t addr,
+                                               unsigned int len,
                                                unsigned int index)
 {
        unsigned int num_cache_lines = num_cache_lines_touched(addr, len);
@@ -163,5 +161,5 @@ unsigned int vnic_wq_error_status(struct vnic_wq *wq);
 void vnic_wq_enable(struct vnic_wq *wq);
 int vnic_wq_disable(struct vnic_wq *wq);
 void vnic_wq_clean(struct vnic_wq *wq,
-                  void (*buf_clean)(struct vnic_wq_buf *buf));
+                  void (*buf_clean)(struct rte_mbuf **buf));
 #endif /* _VNIC_WQ_H_ */