#include "vnic_enet.h"
#include "enic.h"
-int enicpmd_logtype_init;
-int enicpmd_logtype_flow;
-
-#define ENICPMD_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>")
+int enic_pmd_logtype;
/*
* The set of PCI devices this driver supports
*/
#define CISCO_PCI_VENDOR_ID 0x1137
static const struct rte_pci_id pci_id_enic_map[] = {
- { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET) },
- { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
+ {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)},
+ {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)},
+ {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)},
{.vendor_id = 0, /* sentinel */},
};
+/* Supported link speeds of production VIC models */
+static const struct vic_speed_capa {
+ uint16_t sub_devid;
+ uint32_t capa;
+} vic_speed_capa_map[] = {
+ { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */
+ { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */
+ { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */
+ { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */
+ { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */
+ { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */
+ { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */
+ { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */
+ { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */
+ { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */
+ { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */
+ { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */
+ { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */
+ { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */
+ { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
+ ETH_LINK_SPEED_40G }, /* 1440 Mezz */
+ { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
+ ETH_LINK_SPEED_40G }, /* 1480 MLOM */
+ { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */
+ { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */
+ { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */
+ { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */
+ { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */
+ { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */
+ { 0, 0 }, /* End marker */
+};
+
#define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay"
#define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx"
+#define ENIC_DEVARG_GENEVE_OPT "geneve-opt"
#define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite"
RTE_INIT(enicpmd_init_log)
{
- enicpmd_logtype_init = rte_log_register("pmd.net.enic.init");
- if (enicpmd_logtype_init >= 0)
- rte_log_set_level(enicpmd_logtype_init, RTE_LOG_NOTICE);
- enicpmd_logtype_flow = rte_log_register("pmd.net.enic.flow");
- if (enicpmd_logtype_flow >= 0)
- rte_log_set_level(enicpmd_logtype_flow, RTE_LOG_NOTICE);
+ enic_pmd_logtype = rte_log_register("pmd.net.enic");
+ if (enic_pmd_logtype >= 0)
+ rte_log_set_level(enic_pmd_logtype, RTE_LOG_INFO);
}
static int
enum rte_filter_op filter_op,
void *arg)
{
+ struct enic *enic = pmd_priv(dev);
int ret = 0;
ENICPMD_FUNC_TRACE();
+ /*
+ * Currently, when Geneve with options offload is enabled, host
+ * cannot insert match-action rules.
+ */
+ if (enic->geneve_opt_enabled)
+ return -ENOTSUP;
switch (filter_type) {
case RTE_ETH_FILTER_GENERIC:
if (filter_op != RTE_ETH_FILTER_GET)
static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev,
__rte_unused int wait_to_complete)
{
- struct enic *enic = pmd_priv(eth_dev);
-
ENICPMD_FUNC_TRACE();
- return enic_link_update(enic);
+ return enic_link_update(eth_dev);
}
static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev,
return enic_dev_stats_get(enic, stats);
}
-static void enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev)
+static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev)
{
struct enic *enic = pmd_priv(eth_dev);
ENICPMD_FUNC_TRACE();
- enic_dev_stats_clear(enic);
+ return enic_dev_stats_clear(enic);
}
-static void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
+static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev)
+{
+ const struct vic_speed_capa *m;
+ struct rte_pci_device *pdev;
+ uint16_t id;
+
+ pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
+ id = pdev->id.subsystem_device_id;
+ for (m = vic_speed_capa_map; m->sub_devid != 0; m++) {
+ if (m->sub_devid == id)
+ return m->capa;
+ }
+ /* 1300 and later models are at least 40G */
+ if (id >= 0x0100)
+ return ETH_LINK_SPEED_40G;
+ return ETH_LINK_SPEED_10G;
+}
+
+static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,
struct rte_eth_dev_info *device_info)
{
struct enic *enic = pmd_priv(eth_dev);
*/
device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu);
device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS;
+ device_info->min_mtu = ENIC_MIN_MTU;
+ device_info->max_mtu = enic->max_mtu;
device_info->rx_offload_capa = enic->rx_offload_capa;
device_info->tx_offload_capa = enic->tx_offload_capa;
device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa;
ENIC_DEFAULT_TX_RING_SIZE),
.nb_queues = ENIC_DEFAULT_TX_RINGS,
};
+ device_info->speed_capa = speed_capa_from_pci_id(eth_dev);
+
+ return 0;
}
static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev)
return NULL;
}
-static void enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
+static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
{
struct enic *enic = pmd_priv(eth_dev);
+ int ret;
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
- return;
+ return -E_RTE_SECONDARY;
ENICPMD_FUNC_TRACE();
enic->promisc = 1;
- enic_add_packet_filter(enic);
+ ret = enic_add_packet_filter(enic);
+ if (ret != 0)
+ enic->promisc = 0;
+
+ return ret;
}
-static void enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
+static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
{
struct enic *enic = pmd_priv(eth_dev);
+ int ret;
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
- return;
+ return -E_RTE_SECONDARY;
ENICPMD_FUNC_TRACE();
enic->promisc = 0;
- enic_add_packet_filter(enic);
+ ret = enic_add_packet_filter(enic);
+ if (ret != 0)
+ enic->promisc = 1;
+
+ return ret;
}
-static void enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
+static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
{
struct enic *enic = pmd_priv(eth_dev);
+ int ret;
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
- return;
+ return -E_RTE_SECONDARY;
ENICPMD_FUNC_TRACE();
enic->allmulti = 1;
- enic_add_packet_filter(enic);
+ ret = enic_add_packet_filter(enic);
+ if (ret != 0)
+ enic->allmulti = 0;
+
+ return ret;
}
-static void enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
+static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
{
struct enic *enic = pmd_priv(eth_dev);
+ int ret;
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
- return;
+ return -E_RTE_SECONDARY;
ENICPMD_FUNC_TRACE();
enic->allmulti = 0;
- enic_add_packet_filter(enic);
+ ret = enic_add_packet_filter(enic);
+ if (ret != 0)
+ enic->allmulti = 1;
+
+ return ret;
}
static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev,
static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add)
{
- char mac_str[ETHER_ADDR_FMT_SIZE];
+ char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
- rte_ether_format_addr(mac_str, ETHER_ADDR_FMT_SIZE, addr);
- PMD_INIT_LOG(DEBUG, " %s address %s\n",
+ rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
+ ENICPMD_LOG(DEBUG, " %s address %s\n",
add ? "add" : "remove", mac_str);
}
uint32_t nb_mc_addr)
{
struct enic *enic = pmd_priv(eth_dev);
- char mac_str[ETHER_ADDR_FMT_SIZE];
+ char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
struct rte_ether_addr *addr;
uint32_t i, j;
int ret;
if (!rte_is_multicast_ether_addr(addr) ||
rte_is_broadcast_ether_addr(addr)) {
rte_ether_format_addr(mac_str,
- ETHER_ADDR_FMT_SIZE, addr);
- PMD_INIT_LOG(ERR, " invalid multicast address %s\n",
+ RTE_ETHER_ADDR_FMT_SIZE, addr);
+ ENICPMD_LOG(ERR, " invalid multicast address %s\n",
mac_str);
return -EINVAL;
}
/* Flush all if requested */
if (nb_mc_addr == 0 || mc_addr_set == NULL) {
- PMD_INIT_LOG(DEBUG, " flush multicast addresses\n");
+ ENICPMD_LOG(DEBUG, " flush multicast addresses\n");
for (i = 0; i < enic->mc_count; i++) {
addr = &enic->mc_addrs[i];
debug_log_add_del_addr(addr, false);
}
if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) {
- PMD_INIT_LOG(ERR, " too many multicast addresses: max=%d\n",
+ ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n",
ENIC_MULTICAST_PERFECT_FILTERS);
return -ENOSPC;
}
if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN)
return -ENOTSUP;
if (!enic->overlay_offload) {
- PMD_INIT_LOG(DEBUG, " vxlan (overlay offload) is not "
+ ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not "
"supported\n");
return -ENOTSUP;
}
if (vnic_dev_overlay_offload_cfg(enic->vdev,
OVERLAY_CFG_VXLAN_PORT_UPDATE,
port)) {
- PMD_INIT_LOG(DEBUG, " failed to update vxlan port\n");
+ ENICPMD_LOG(DEBUG, " failed to update vxlan port\n");
return -EINVAL;
}
- PMD_INIT_LOG(DEBUG, " updated vxlan port to %u\n", port);
+ ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port);
enic->vxlan_port = port;
return 0;
}
* number replaces it.
*/
if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) {
- PMD_INIT_LOG(DEBUG, " %u is already configured or invalid\n",
+ ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n",
tnl->udp_port);
return -EINVAL;
}
* which is tied to inner RSS and TSO.
*/
if (tnl->udp_port != enic->vxlan_port) {
- PMD_INIT_LOG(DEBUG, " %u is not a configured vxlan port\n",
+ ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n",
tnl->udp_port);
return -EINVAL;
}
enic->disable_overlay = b;
if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0)
enic->enable_avx2_rx = b;
+ if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0)
+ enic->geneve_opt_request = b;
return 0;
}
static const char *const valid_keys[] = {
ENIC_DEVARG_DISABLE_OVERLAY,
ENIC_DEVARG_ENABLE_AVX2_RX,
+ ENIC_DEVARG_GENEVE_OPT,
ENIC_DEVARG_IG_VLAN_REWRITE,
NULL};
struct enic *enic = pmd_priv(dev);
enic->disable_overlay = false;
enic->enable_avx2_rx = false;
+ enic->geneve_opt_request = false;
enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
if (!dev->device->devargs)
return 0;
enic_parse_zero_one, enic) < 0 ||
rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX,
enic_parse_zero_one, enic) < 0 ||
+ rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT,
+ enic_parse_zero_one, enic) < 0 ||
rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE,
enic_parse_ig_vlan_rewrite, enic) < 0) {
rte_kvargs_free(kvlist);
ENICPMD_FUNC_TRACE();
- enic->port_id = eth_dev->data->port_id;
- enic->rte_dev = eth_dev;
eth_dev->dev_ops = &enicpmd_eth_dev_ops;
eth_dev->rx_pkt_burst = &enic_recv_pkts;
eth_dev->tx_pkt_burst = &enic_xmit_pkts;
eth_dev->tx_pkt_prepare = &enic_prep_pkts;
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
+ enic_pick_tx_handler(eth_dev);
+ enic_pick_rx_handler(eth_dev);
+ return 0;
+ }
+ /* Only the primary sets up adapter and other data in shared memory */
+ enic->port_id = eth_dev->data->port_id;
+ enic->rte_dev = eth_dev;
+ enic->dev_data = eth_dev->data;
/* Let rte_eth_dev_close() release the port resources */
eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
static struct rte_pci_driver rte_enic_pmd = {
.id_table = pci_id_enic_map,
- .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
- RTE_PCI_DRV_IOVA_AS_VA,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
.probe = eth_enic_pci_probe,
.remove = eth_enic_pci_remove,
};
RTE_PMD_REGISTER_PARAM_STRING(net_enic,
ENIC_DEVARG_DISABLE_OVERLAY "=0|1 "
ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 "
+ ENIC_DEVARG_GENEVE_OPT "=0|1 "
ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass");
git.droids-corp.org / dpdk.git / blobdiff