#include "vnic_enet.h"
#include "enic.h"
-int enic_pmd_logtype;
-
/*
* The set of PCI devices this driver supports
*/
#define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay"
#define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx"
+#define ENIC_DEVARG_GENEVE_OPT "geneve-opt"
#define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite"
-RTE_INIT(enicpmd_init_log)
-{
- enic_pmd_logtype = rte_log_register("pmd.net.enic");
- if (enic_pmd_logtype >= 0)
- rte_log_set_level(enic_pmd_logtype, RTE_LOG_INFO);
-}
+RTE_LOG_REGISTER(enic_pmd_logtype, pmd.net.enic, INFO);
static int
enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev,
enum rte_filter_op filter_op,
void *arg)
{
+ struct enic *enic = pmd_priv(dev);
int ret = 0;
ENICPMD_FUNC_TRACE();
+ /*
+ * Currently, when Geneve with options offload is enabled, host
+ * cannot insert match-action rules.
+ */
+ if (enic->geneve_opt_enabled)
+ return -ENOTSUP;
switch (filter_type) {
case RTE_ETH_FILTER_GENERIC:
if (filter_op != RTE_ETH_FILTER_GET)
return -EINVAL;
- *(const void **)arg = &enic_flow_ops;
+ if (enic->flow_filter_mode == FILTER_FLOWMAN)
+ *(const void **)arg = &enic_fm_flow_ops;
+ else
+ *(const void **)arg = &enic_flow_ops;
break;
case RTE_ETH_FILTER_FDIR:
ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg);
enic->ig_vlan_strip_en = 0;
}
- if ((mask & ETH_VLAN_FILTER_MASK) &&
- (offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
- dev_warning(enic,
- "Configuration of VLAN filter is not supported\n");
- }
-
- if ((mask & ETH_VLAN_EXTEND_MASK) &&
- (offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)) {
- dev_warning(enic,
- "Configuration of extended VLAN is not supported\n");
- }
-
return enic_set_vlan_strip(enic);
}
return ret;
}
+ if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
+ eth_dev->data->dev_conf.rxmode.offloads |=
+ DEV_RX_OFFLOAD_RSS_HASH;
+
enic->mc_count = 0;
enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads &
DEV_RX_OFFLOAD_CHECKSUM);
static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev,
__rte_unused int wait_to_complete)
{
- struct enic *enic = pmd_priv(eth_dev);
-
ENICPMD_FUNC_TRACE();
- return enic_link_update(enic);
+ return enic_link_update(eth_dev);
}
static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev,
/* 1300 and later models are at least 40G */
if (id >= 0x0100)
return ETH_LINK_SPEED_40G;
+ /* VFs have subsystem id 0, check device id */
+ if (id == 0) {
+ /* Newer VF implies at least 40G model */
+ if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN)
+ return ETH_LINK_SPEED_40G;
+ }
return ETH_LINK_SPEED_10G;
}
ENICPMD_FUNC_TRACE();
sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id);
- data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id);
+ data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic);
rq_sop = &enic->rq[sop_queue_idx];
rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */
qinfo->mp = rq_sop->mp;
/* tx_thresh, and all the other fields are not applicable for enic */
}
+static int enicpmd_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
+ __rte_unused uint16_t queue_id,
+ struct rte_eth_burst_mode *mode)
+{
+ eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
+ struct enic *enic = pmd_priv(dev);
+ const char *info_str = NULL;
+ int ret = -EINVAL;
+
+ ENICPMD_FUNC_TRACE();
+ if (enic->use_noscatter_vec_rx_handler)
+ info_str = "Vector AVX2 No Scatter";
+ else if (pkt_burst == enic_noscatter_recv_pkts)
+ info_str = "Scalar No Scatter";
+ else if (pkt_burst == enic_recv_pkts)
+ info_str = "Scalar";
+ if (info_str) {
+ strlcpy(mode->info, info_str, sizeof(mode->info));
+ ret = 0;
+ }
+ return ret;
+}
+
+static int enicpmd_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
+ __rte_unused uint16_t queue_id,
+ struct rte_eth_burst_mode *mode)
+{
+ eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
+ const char *info_str = NULL;
+ int ret = -EINVAL;
+
+ ENICPMD_FUNC_TRACE();
+ if (pkt_burst == enic_simple_xmit_pkts)
+ info_str = "Scalar Simplified";
+ else if (pkt_burst == enic_xmit_pkts)
+ info_str = "Scalar";
+ if (info_str) {
+ strlcpy(mode->info, info_str, sizeof(mode->info));
+ ret = 0;
+ }
+ return ret;
+}
+
static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
uint16_t rx_queue_id)
{
tnl->udp_port);
return -EINVAL;
}
- return update_vxlan_port(enic, ENIC_DEFAULT_VXLAN_PORT);
+ return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT);
}
static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev,
.rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable,
.rxq_info_get = enicpmd_dev_rxq_info_get,
.txq_info_get = enicpmd_dev_txq_info_get,
+ .rx_burst_mode_get = enicpmd_dev_rx_burst_mode_get,
+ .tx_burst_mode_get = enicpmd_dev_tx_burst_mode_get,
.dev_led_on = NULL,
.dev_led_off = NULL,
.flow_ctrl_get = NULL,
enic->disable_overlay = b;
if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0)
enic->enable_avx2_rx = b;
+ if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0)
+ enic->geneve_opt_request = b;
return 0;
}
static const char *const valid_keys[] = {
ENIC_DEVARG_DISABLE_OVERLAY,
ENIC_DEVARG_ENABLE_AVX2_RX,
+ ENIC_DEVARG_GENEVE_OPT,
ENIC_DEVARG_IG_VLAN_REWRITE,
NULL};
struct enic *enic = pmd_priv(dev);
enic->disable_overlay = false;
enic->enable_avx2_rx = false;
+ enic->geneve_opt_request = false;
enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU;
if (!dev->device->devargs)
return 0;
enic_parse_zero_one, enic) < 0 ||
rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX,
enic_parse_zero_one, enic) < 0 ||
+ rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT,
+ enic_parse_zero_one, enic) < 0 ||
rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE,
enic_parse_ig_vlan_rewrite, enic) < 0) {
rte_kvargs_free(kvlist);
ENICPMD_FUNC_TRACE();
- enic->port_id = eth_dev->data->port_id;
- enic->rte_dev = eth_dev;
eth_dev->dev_ops = &enicpmd_eth_dev_ops;
eth_dev->rx_pkt_burst = &enic_recv_pkts;
eth_dev->tx_pkt_burst = &enic_xmit_pkts;
eth_dev->tx_pkt_prepare = &enic_prep_pkts;
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
+ enic_pick_tx_handler(eth_dev);
+ enic_pick_rx_handler(eth_dev);
+ return 0;
+ }
+ /* Only the primary sets up adapter and other data in shared memory */
+ enic->port_id = eth_dev->data->port_id;
+ enic->rte_dev = eth_dev;
+ enic->dev_data = eth_dev->data;
/* Let rte_eth_dev_close() release the port resources */
eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
.remove = eth_enic_pci_remove,
};
+int dev_is_enic(struct rte_eth_dev *dev)
+{
+ return dev->device->driver == &rte_enic_pmd.driver;
+}
+
RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd);
RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map);
RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(net_enic,
ENIC_DEVARG_DISABLE_OVERLAY "=0|1 "
ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 "
+ ENIC_DEVARG_GENEVE_OPT "=0|1 "
ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass");
git.droids-corp.org / dpdk.git / blobdiff