struct vnic_rq *data_rq;
for (index = 0; index < enic->rq_count; index++) {
+ cq_idx = enic_cq_rq(enic, enic_sop_rq(index));
+
vnic_rq_init(&enic->rq[enic_sop_rq(index)],
- enic_cq_rq(enic, index),
+ cq_idx,
error_interrupt_enable,
error_interrupt_offset);
data_rq = &enic->rq[enic_data_rq(index)];
if (data_rq->in_use)
vnic_rq_init(data_rq,
- enic_cq_rq(enic, index),
+ cq_idx,
error_interrupt_enable,
error_interrupt_offset);
- cq_idx = enic_cq_rq(enic, index);
vnic_cq_init(&enic->cq[cq_idx],
0 /* flow_control_enable */,
1 /* color_enable */,
dev_debug(enic, "port=%u, qidx=%u, Write %u posted idx, %u sw held\n",
enic->port_id, rq->index, rq->posted_index, rq->rx_nb_hold);
iowrite32(rq->posted_index, &rq->ctrl->posted_index);
+ iowrite32(0, &rq->ctrl->fetch_index);
rte_rmb();
return 0;
return -ENOMEM;
for (i = 0; i < (1 << rss_hash_bits); i++)
- (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;
+ (*rss_cpu_buf_va).cpu[i / 4].b[i % 4] =
+ enic_sop_rq(i % enic->rq_count);
err = enic_set_rss_cpu(enic,
rss_cpu_buf_pa,
/* With Rx scatter support, two RQs are now used per RQ used by
* the application.
*/
- if (enic->rq_count < (eth_dev->data->nb_rx_queues * 2)) {
+ if (enic->conf_rq_count < eth_dev->data->nb_rx_queues) {
dev_err(dev, "Not enough Receive queues. Requested:%u which uses %d RQs on VIC, Configured:%u\n",
eth_dev->data->nb_rx_queues,
- eth_dev->data->nb_rx_queues * 2, enic->rq_count);
+ eth_dev->data->nb_rx_queues * 2, enic->conf_rq_count);
rc = -EINVAL;
}
- if (enic->wq_count < eth_dev->data->nb_tx_queues) {
+ if (enic->conf_wq_count < eth_dev->data->nb_tx_queues) {
dev_err(dev, "Not enough Transmit queues. Requested:%u, Configured:%u\n",
- eth_dev->data->nb_tx_queues, enic->wq_count);
+ eth_dev->data->nb_tx_queues, enic->conf_wq_count);
rc = -EINVAL;
}
- if (enic->cq_count < (enic->rq_count + enic->wq_count)) {
+ if (enic->conf_cq_count < (eth_dev->data->nb_rx_queues +
+ eth_dev->data->nb_tx_queues)) {
dev_err(dev, "Not enough Completion queues. Required:%u, Configured:%u\n",
- enic->rq_count + enic->wq_count, enic->cq_count);
+ (eth_dev->data->nb_rx_queues +
+ eth_dev->data->nb_tx_queues), enic->conf_cq_count);
rc = -EINVAL;
}