fm10k/base: fix VF multicast update

[dpdk.git] / drivers / net / fm10k / base / fm10k_pf.c

diff --git a/drivers/net/fm10k/base/fm10k_pf.c b/drivers/net/fm10k/base/fm10k_pf.c
index 3545a24..29ef6a9 100644 (file)
--- a/drivers/net/fm10k/base/fm10k_pf.c
+++ b/drivers/net/fm10k/base/fm10k_pf.c
@@ -169,19 +169,26 @@ STATIC s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
                                FM10K_TPH_RXCTRL_HDR_WROEN);
        }
 
-       /* set max hold interval to align with 1.024 usec in all modes */
+       /* set max hold interval to align with 1.024 usec in all modes and
+        * store ITR scale
+        */
        switch (hw->bus.speed) {
        case fm10k_bus_speed_2500:
                dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
+               hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1;
                break;
        case fm10k_bus_speed_5000:
                dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
+               hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2;
                break;
        case fm10k_bus_speed_8000:
                dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
+               hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
                break;
        default:
                dma_ctrl = 0;
+               /* just in case, assume Gen3 ITR scale */
+               hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
                break;
        }
 
@@ -360,6 +367,9 @@ STATIC s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
 
        DEBUGFUNC("fm10k_update_xc_addr_pf");
 
+       /* clear set bit from VLAN ID */
+       vid &= ~FM10K_VLAN_CLEAR;
+
        /* if glort or VLAN are not valid return error */
        if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
                return FM10K_ERR_PARAM;
@@ -716,7 +726,8 @@ STATIC s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
        /* loop through unallocated rings assigning them back to PF */
        for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
                FM10K_WRITE_REG(hw, FM10K_TXDCTL(i), 0);
-               FM10K_WRITE_REG(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | vid);
+               FM10K_WRITE_REG(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF |
+                               FM10K_TXQCTL_UNLIMITED_BW | vid);
                FM10K_WRITE_REG(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
        }
 
@@ -946,6 +957,12 @@ STATIC s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
        FM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx), tdbal);
        FM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx), tdbah);
 
+       /* Provide the VF the ITR scale, using software-defined fields in TDLEN
+        * to pass the information during VF initialization
+        */
+       FM10K_WRITE_REG(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale <<
+                                                  FM10K_TDLEN_ITR_SCALE_SHIFT);
+
 err_out:
        /* configure Queue control register */
        txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
@@ -1078,6 +1095,9 @@ STATIC s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
        for (i = queues_per_pool; i--;) {
                FM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
                FM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
+               FM10K_WRITE_REG(hw, FM10K_TDLEN(vf_q_idx + i),
+                               hw->mac.itr_scale <<
+                               FM10K_TDLEN_ITR_SCALE_SHIFT);
                FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
                FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
        }
@@ -1298,8 +1318,8 @@ s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
                }
 
                /* notify switch of request for new multicast address */
-               err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac,
-                                                !(vlan & FM10K_VLAN_CLEAR), 0);
+               err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac, vlan,
+                                                !(vlan & FM10K_VLAN_CLEAR));
        }
 
        return err;
@@ -1810,6 +1830,12 @@ const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {
        FM10K_TLV_ATTR_LAST
 };
 
+const struct fm10k_tlv_attr fm10k_tx_timestamp_mode_attr[] = {
+       FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_TIMESTAMP_MODE_RESP,
+                                sizeof(struct fm10k_swapi_tx_timestamp_mode)),
+       FM10K_TLV_ATTR_LAST
+};
+
 /* currently there is no shared 1588 timestamp handler */
 
 /**
@@ -1868,7 +1894,7 @@ STATIC s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)
 {
        u64 systime_adjust;
 
-       DEBUGFUNC("fm10k_adjust_systime_vf");
+       DEBUGFUNC("fm10k_adjust_systime_pf");
 
        /* if sw_addr is not set we don't have switch register access */
        if (!hw->sw_addr)