STATIC s32 fm10k_stop_hw_vf(struct fm10k_hw *hw)
{
u8 *perm_addr = hw->mac.perm_addr;
- u32 bal = 0, bah = 0;
+ u32 bal = 0, bah = 0, tdlen;
s32 err;
u16 i;
((u32)perm_addr[2]);
}
+ /* restore default itr_scale for next VF initialization */
+ tdlen = hw->mac.itr_scale << FM10K_TDLEN_ITR_SCALE_SHIFT;
+
/* The queues have already been disabled so we just need to
* update their base address registers
*/
FM10K_WRITE_REG(hw, FM10K_TDBAH(i), bah);
FM10K_WRITE_REG(hw, FM10K_RDBAL(i), bal);
FM10K_WRITE_REG(hw, FM10K_RDBAH(i), bah);
+ /* Restore ITR scale in software-defined mechanism in TDLEN
+ * for next VF initialization. See definition of
+ * FM10K_TDLEN_ITR_SCALE_SHIFT for more details on the use of
+ * TDLEN here.
+ */
+ FM10K_WRITE_REG(hw, FM10K_TDLEN(i), tdlen);
}
return FM10K_SUCCESS;
DEBUGFUNC("fm10k_init_hw_vf");
- /* assume we always have at least 1 queue */
+ /* verify we have at least 1 queue */
+ if (!~FM10K_READ_REG(hw, FM10K_TXQCTL(0)) ||
+ !~FM10K_READ_REG(hw, FM10K_RXQCTL(0))) {
+ err = FM10K_ERR_NO_RESOURCES;
+ goto reset_max_queues;
+ }
+
+ /* determine how many queues we have */
for (i = 1; tqdloc0 && (i < FM10K_MAX_QUEUES_POOL); i++) {
/* verify the Descriptor cache offsets are increasing */
tqdloc = ~FM10K_READ_REG(hw, FM10K_TQDLOC(i));
/* shut down queues we own and reset DMA configuration */
err = fm10k_disable_queues_generic(hw, i);
if (err)
- return err;
+ goto reset_max_queues;
/* record maximum queue count */
hw->mac.max_queues = i;
- /* fetch default VLAN */
+ /* fetch default VLAN and ITR scale */
hw->mac.default_vid = (FM10K_READ_REG(hw, FM10K_TXQCTL(0)) &
FM10K_TXQCTL_VID_MASK) >> FM10K_TXQCTL_VID_SHIFT;
+ /* Read the ITR scale from TDLEN. See the definition of
+ * FM10K_TDLEN_ITR_SCALE_SHIFT for more information about how TDLEN is
+ * used here.
+ */
+ hw->mac.itr_scale = (FM10K_READ_REG(hw, FM10K_TDLEN(0)) &
+ FM10K_TDLEN_ITR_SCALE_MASK) >>
+ FM10K_TDLEN_ITR_SCALE_SHIFT;
return FM10K_SUCCESS;
+
+reset_max_queues:
+ hw->mac.max_queues = 0;
+
+ return err;
}
/**
}
const struct fm10k_tlv_attr fm10k_1588_msg_attr[] = {
- FM10K_TLV_ATTR_U64(FM10K_1588_MSG_TIMESTAMP),
+ FM10K_TLV_ATTR_U64(FM10K_1588_MSG_CLK_OFFSET),
FM10K_TLV_ATTR_LAST
};
-/* currently there is no shared 1588 timestamp handler */
+/* currently there is no shared 1588 message handler */
/**
* fm10k_update_hw_stats_vf - Updates hardware related statistics of VF
return FM10K_SUCCESS;
}
-/**
- * fm10k_request_tx_timestamp_mode_vf - Request Tx timestamp mode
- * @hw: pointer to hardware structure
- * @glort: glort to request Tx timestamps for
- * @mode: timestamp mode to request
- *
- * This function takes the requested timestamp mode and verifies that it was
- * requested as none since the VF cannot support receipt of Tx timestamps.
- *
- * If the mode is non-zero ERR_PARAM, else success
- **/
-STATIC s32 fm10k_request_tx_timestamp_mode_vf(struct fm10k_hw *hw,
- u16 glort,
- u8 mode)
-{
- UNREFERENCED_2PARAMETER(hw, glort);
-
- return mode ? FM10K_ERR_PARAM : FM10K_SUCCESS;
-}
-
/**
* fm10k_adjust_systime_vf - Adjust systime frequency
* @hw: pointer to hardware structure
mac->ops.get_host_state = &fm10k_get_host_state_generic;
mac->ops.adjust_systime = &fm10k_adjust_systime_vf;
mac->ops.read_systime = &fm10k_read_systime_vf;
- mac->ops.request_tx_timestamp_mode = &fm10k_request_tx_timestamp_mode_vf;
mac->max_msix_vectors = fm10k_get_pcie_msix_count_generic(hw);