#ifndef _HINIC_PORT_CMD_H_
#define _HINIC_PORT_CMD_H_
-enum hinic_eq_type {
- HINIC_AEQ,
- HINIC_CEQ
-};
+#define HINIC_AEQ 0
enum hinic_resp_aeq_num {
HINIC_AEQ0 = 0,
HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE = 0x4a,
HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE,
+ HINIC_PORT_CMD_GET_MGMT_VERSION = 0x58,
+
HINIC_PORT_CMD_GET_PORT_TYPE = 0x5b,
HINIC_PORT_CMD_GET_VPORT_ENABLE = 0x5c,
HINIC_PORT_CMD_GET_PORT_INFO = 0xaa,
+ HINIC_PORT_CMD_UP_TC_ADD_FLOW = 0xaf,
+ HINIC_PORT_CMD_UP_TC_DEL_FLOW = 0xb0,
+ HINIC_PORT_CMD_UP_TC_GET_FLOW = 0xb1,
+ HINIC_PORT_CMD_UP_TC_FLUSH_TCAM = 0xb2,
+ HINIC_PORT_CMD_UP_TC_CTRL_TCAM_BLOCK = 0xb3,
+ HINIC_PORT_CMD_UP_TC_ENABLE = 0xb4,
+
HINIC_PORT_CMD_SET_IPSU_MAC = 0xcb,
HINIC_PORT_CMD_GET_IPSU_MAC = 0xcc,
+ HINIC_PORT_CMD_SET_XSFP_STATUS = 0xD4,
+
HINIC_PORT_CMD_GET_LINK_MODE = 0xD9,
HINIC_PORT_CMD_SET_SPEED = 0xDA,
HINIC_PORT_CMD_SET_AUTONEG = 0xDB,
HINIC_PORT_CMD_SET_VHD_CFG = 0xF7,
HINIC_PORT_CMD_SET_LINK_FOLLOW = 0xF8,
+ HINIC_PORT_CMD_Q_FILTER = 0xFC,
+ HINIC_PORT_CMD_TCAM_FILTER = 0xFE,
+ HINIC_PORT_CMD_SET_VLAN_FILTER = 0xFF
};
/* cmd of mgmt CPU message for HW module */