return retval;
}
-static void hns3_parse_capability(struct hns3_hw *hw,
- struct hns3_query_version_cmd *cmd)
+static void
+hns3_parse_capability(struct hns3_hw *hw,
+ struct hns3_query_version_cmd *cmd)
{
uint32_t caps = rte_le_to_cpu_32(cmd->caps[0]);
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_STASH_B))
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_STASH_B, 1);
+ if (hns3_get_bit(caps, HNS3_CAPS_RXD_ADV_LAYOUT_B))
+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
+ 1);
+ if (hns3_get_bit(caps, HNS3_CAPS_UDP_TUNNEL_CSUM_B))
+ hns3_set_bit(hw->capability,
+ HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1);
}
static uint32_t
void
hns3_cmd_uninit(struct hns3_hw *hw)
{
+ __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+
+ /*
+ * A delay is added to ensure that the register cleanup operations
+ * will not be performed concurrently with the firmware command and
+ * ensure that all the reserved commands are executed.
+ * Concurrency may occur in two scenarios: asynchronous command and
+ * timeout command. If the command fails to be executed due to busy
+ * scheduling, the command will be processed in the next scheduling
+ * of the firmware.
+ */
+ rte_delay_ms(HNS3_CMDQ_CLEAR_WAIT_TIME);
+
rte_spinlock_lock(&hw->cmq.csq.lock);
rte_spinlock_lock(&hw->cmq.crq.lock);
- __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
hns3_cmd_clear_regs(hw);
rte_spinlock_unlock(&hw->cmq.crq.lock);
rte_spinlock_unlock(&hw->cmq.csq.lock);