net/hns3: fix rollback in PF init

[dpdk.git] / drivers / net / hns3 / hns3_cmd.c

diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
index 3d6ffc0..1d8ef7a 100644 (file)
--- a/drivers/net/hns3/hns3_cmd.c
+++ b/drivers/net/hns3/hns3_cmd.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2019 Hisilicon Limited.
+ * Copyright(c) 2018-2021 HiSilicon Limited.
  */
 
 #include <ethdev_pci.h>
@@ -195,12 +195,14 @@ hns3_cmd_csq_clean(struct hns3_hw *hw)
 {
        struct hns3_cmq_ring *csq = &hw->cmq.csq;
        uint32_t head;
+       uint32_t addr;
        int clean;
 
        head = hns3_read_dev(hw, HNS3_CMDQ_TX_HEAD_REG);
-       if (!is_valid_csq_clean_head(csq, head)) {
-               hns3_err(hw, "wrong cmd head (%u, %u-%u)", head,
-                           csq->next_to_use, csq->next_to_clean);
+       addr = hns3_read_dev(hw, HNS3_CMDQ_TX_ADDR_L_REG);
+       if (!is_valid_csq_clean_head(csq, head) || addr == 0) {
+               hns3_err(hw, "wrong cmd addr(%0x) head (%u, %u-%u)", addr, head,
+                        csq->next_to_use, csq->next_to_clean);
                if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
                        __atomic_store_n(&hw->reset.disable_cmd, 1,
                                         __ATOMIC_RELAXED);
@@ -409,8 +411,9 @@ hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num)
        return retval;
 }
 
-static void hns3_parse_capability(struct hns3_hw *hw,
-                                 struct hns3_query_version_cmd *cmd)
+static void
+hns3_parse_capability(struct hns3_hw *hw,
+                     struct hns3_query_version_cmd *cmd)
 {
        uint32_t caps = rte_le_to_cpu_32(cmd->caps[0]);
 
@@ -429,6 +432,12 @@ static void hns3_parse_capability(struct hns3_hw *hw,
                hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B, 1);
        if (hns3_get_bit(caps, HNS3_CAPS_STASH_B))
                hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_STASH_B, 1);
+       if (hns3_get_bit(caps, HNS3_CAPS_RXD_ADV_LAYOUT_B))
+               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
+                            1);
+       if (hns3_get_bit(caps, HNS3_CAPS_UDP_TUNNEL_CSUM_B))
+               hns3_set_bit(hw->capability,
+                               HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1);
 }
 
 static uint32_t
@@ -582,9 +591,21 @@ hns3_cmd_destroy_queue(struct hns3_hw *hw)
 void
 hns3_cmd_uninit(struct hns3_hw *hw)
 {
+       __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+
+       /*
+        * A delay is added to ensure that the register cleanup operations
+        * will not be performed concurrently with the firmware command and
+        * ensure that all the reserved commands are executed.
+        * Concurrency may occur in two scenarios: asynchronous command and
+        * timeout command. If the command fails to be executed due to busy
+        * scheduling, the command will be processed in the next scheduling
+        * of the firmware.
+        */
+       rte_delay_ms(HNS3_CMDQ_CLEAR_WAIT_TIME);
+
        rte_spinlock_lock(&hw->cmq.csq.lock);
        rte_spinlock_lock(&hw->cmq.crq.lock);
-       __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
        hns3_cmd_clear_regs(hw);
        rte_spinlock_unlock(&hw->cmq.crq.lock);
        rte_spinlock_unlock(&hw->cmq.csq.lock);