} dev_caps[] = {
{ HNS3_CAPS_FD_QUEUE_REGION_B, "fd_queue_region" },
{ HNS3_CAPS_PTP_B, "ptp" },
+ { HNS3_CAPS_TX_PUSH_B, "tx_push" },
{ HNS3_CAPS_PHY_IMP_B, "phy_imp" },
{ HNS3_CAPS_TQP_TXRX_INDEP_B, "tqp_txrx_indep" },
{ HNS3_CAPS_HW_PAD_B, "hw_pad" },
hns3_warn(hw, "ignore PTP capability due to lack of "
"rxd advanced layout capability.");
}
+ if (hns3_get_bit(caps, HNS3_CAPS_TX_PUSH_B))
+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TX_PUSH_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_PHY_IMP_B))
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_TQP_TXRX_INDEP_B))
static int
hns3_apply_fw_compat_cmd_result(struct hns3_hw *hw, int result)
{
- if (result != 0 && hns3_dev_copper_supported(hw)) {
+ if (result != 0 && hns3_dev_get_support(hw, COPPER)) {
hns3_err(hw, "firmware fails to initialize the PHY, ret = %d.",
result);
return result;
}
if (revision == PCI_REVISION_ID_HIP09_A) {
struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
- if (hns3_dev_copper_supported(hw) == 0 || pf->is_tmp_phy) {
+ if (hns3_dev_get_support(hw, COPPER) == 0 || pf->is_tmp_phy) {
PMD_INIT_LOG(ERR, "***use temp phy driver in dpdk***");
pf->is_tmp_phy = true;
hns3_set_bit(hw->capability,
if (is_init) {
hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
- if (hns3_dev_copper_supported(hw))
+ if (hns3_dev_get_support(hw, COPPER))
hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
}
req->compat = rte_cpu_to_le_32(compat);