hns3_allocate_dma_mem(struct hns3_hw *hw, struct hns3_cmq_ring *ring,
uint64_t size, uint32_t alignment)
{
+ static uint64_t hns3_dma_memzone_id;
const struct rte_memzone *mz = NULL;
char z_name[RTE_MEMZONE_NAMESIZE];
- snprintf(z_name, sizeof(z_name), "hns3_dma_%" PRIu64, rte_rand());
+ snprintf(z_name, sizeof(z_name), "hns3_dma_%" PRIu64,
+ __atomic_fetch_add(&hns3_dma_memzone_id, 1, __ATOMIC_RELAXED));
mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
RTE_MEMZONE_IOVA_CONTIG, alignment,
RTE_PGSIZE_2M);
{ HNS3_CAPS_STASH_B, "stash" },
{ HNS3_CAPS_UDP_TUNNEL_CSUM_B, "udp_tunnel_csum" },
{ HNS3_CAPS_RAS_IMP_B, "ras_imp" },
- { HNS3_CAPS_RXD_ADV_LAYOUT_B, "rxd_adv_layout" }
+ { HNS3_CAPS_RXD_ADV_LAYOUT_B, "rxd_adv_layout" },
+ { HNS3_CAPS_TM_B, "tm_capability" }
};
uint32_t i;
HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_RAS_IMP_B))
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RAS_IMP_B, 1);
+ if (hns3_get_bit(caps, HNS3_CAPS_TM_B))
+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TM_B, 1);
}
static uint32_t