HNS3_OPC_GBL_RST_STATUS = 0x0021,
HNS3_OPC_QUERY_FUNC_STATUS = 0x0022,
HNS3_OPC_QUERY_PF_RSRC = 0x0023,
+ HNS3_OPC_QUERY_VF_RSRC = 0x0024,
HNS3_OPC_GET_CFG_PARAM = 0x0025,
HNS3_OPC_PF_RST_DONE = 0x0026,
uint8_t rsv[2];
};
-#define HNS3_PF_VEC_NUM_S 0
-#define HNS3_PF_VEC_NUM_M GENMASK(7, 0)
+#define HNS3_VEC_NUM_S 0
+#define HNS3_VEC_NUM_M GENMASK(7, 0)
+#define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */
struct hns3_pf_res_cmd {
uint16_t tqp_num;
uint16_t buf_size;
uint32_t rsv[2];
};
+struct hns3_vf_res_cmd {
+ uint16_t tqp_num;
+ uint16_t reserved;
+ uint16_t msixcap_localid_ba_nic;
+ uint16_t msixcap_localid_ba_rocee;
+ uint16_t vf_intr_vector_number;
+ uint16_t rsv[7];
+};
+
#define HNS3_UMV_SPC_ALC_B 0
struct hns3_umv_spc_alc_cmd {
uint8_t allocate;
uint8_t rsv[18];
};
-#define HNS3_RING_TYPE_B 0
-#define HNS3_RING_TYPE_TX 0
-#define HNS3_RING_TYPE_RX 1
+enum hns3_ring_type {
+ HNS3_RING_TYPE_TX,
+ HNS3_RING_TYPE_RX
+};
+
+enum hns3_int_gl_idx {
+ HNS3_RING_GL_RX,
+ HNS3_RING_GL_TX,
+ HNS3_RING_GL_IMMEDIATE = 3
+};
+
#define HNS3_RING_GL_IDX_S 0
#define HNS3_RING_GL_IDX_M GENMASK(1, 0)
-#define HNS3_RING_GL_RX 0
-#define HNS3_RING_GL_TX 1
#define HNS3_VECTOR_ELEMENTS_PER_CMD 10