HNS3_OPC_QUERY_DEV_SPECS = 0x0050,
+ HNS3_OPC_SSU_DROP_REG = 0x0065,
+
/* MAC command */
HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
+ HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310,
+ HNS3_OPC_MAC_TNL_INT_EN = 0x0311,
+ HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312,
HNS3_OPC_CONFIG_FEC_MODE = 0x031A,
/* PFC/Pause commands */
/* Firmware stats command */
HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A,
+ /* Firmware control phy command */
+ HNS3_OPC_PHY_PARAM_CFG = 0x7025,
/* SFP command */
HNS3_OPC_GET_SFP_EEPROM = 0x7100,
HNS3_CAPS_TQP_TXRX_INDEP_B,
HNS3_CAPS_HW_PAD_B,
HNS3_CAPS_STASH_B,
+ HNS3_CAPS_UDP_TUNNEL_CSUM_B,
+ HNS3_CAPS_RAS_IMP_B,
+ HNS3_CAPS_FEC_B,
+ HNS3_CAPS_PAUSE_B,
+ HNS3_CAPS_RXD_ADV_LAYOUT_B,
};
enum HNS3_API_CAP_BITS {
#define HNS3_LINK_EVENT_REPORT_EN_B 0
#define HNS3_NCSI_ERROR_REPORT_EN_B 1
+#define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2
struct hns3_firmware_compat_cmd {
uint32_t compat;
uint8_t rsv[20];
};
+/* Bitmap flags in supported, advertising and lp_advertising */
+#define HNS3_PHY_LINK_SPEED_10M_HD_BIT BIT(0)
+#define HNS3_PHY_LINK_SPEED_10M_BIT BIT(1)
+#define HNS3_PHY_LINK_SPEED_100M_HD_BIT BIT(2)
+#define HNS3_PHY_LINK_SPEED_100M_BIT BIT(3)
+#define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6)
+#define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13)
+#define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14)
+
+#define HNS3_PHY_PARAM_CFG_BD_NUM 2
+struct hns3_phy_params_bd0_cmd {
+ uint32_t speed;
+#define HNS3_PHY_DUPLEX_CFG_B 0
+ uint8_t duplex;
+#define HNS3_PHY_AUTONEG_CFG_B 0
+ uint8_t autoneg;
+ uint8_t eth_tp_mdix;
+ uint8_t eth_tp_mdix_ctrl;
+ uint8_t port;
+ uint8_t transceiver;
+ uint8_t phy_address;
+ uint8_t rsv;
+ uint32_t supported;
+ uint32_t advertising;
+ uint32_t lp_advertising;
+};
+
+struct hns3_phy_params_bd1_cmd {
+ uint8_t master_slave_cfg;
+ uint8_t master_slave_state;
+ uint8_t rsv1[2];
+ uint32_t rsv2[5];
+};
+
#define HNS3_MAC_TX_EN_B 6
#define HNS3_MAC_RX_EN_B 7
#define HNS3_MAC_PAD_TX_B 11
#define HNS3_CFG_RESET_MAC_B 3
#define HNS3_CFG_RESET_FUNC_B 7
+#define HNS3_CFG_RESET_RCB_B 1
struct hns3_reset_cmd {
uint8_t mac_func_reset;
uint8_t fun_reset_vfid;
- uint8_t rsv[22];
+ uint8_t fun_reset_rcb;
+ uint8_t rsv1;
+ uint16_t fun_reset_rcb_vqid_start;
+ uint16_t fun_reset_rcb_vqid_num;
+ uint8_t fun_reset_rcb_return_status;
+ uint8_t rsv2[15];
};
#define HNS3_QUERY_DEV_SPECS_BD_NUM 4
uint32_t rsv2[2];
};
+#define HNS3_OPC_SSU_DROP_REG_NUM 2
+
+struct hns3_query_ssu_cmd {
+ uint8_t rxtx;
+ uint8_t rsv[3];
+ uint32_t full_drop_cnt;
+ uint32_t part_drop_cnt;
+ uint32_t oq_drop_cnt;
+ uint32_t rev1[2];
+};
+
#define HNS3_MAX_TQP_NUM_HIP08_PF 64
#define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
#define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */