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net/mlx5: rearrange creation of WQ and CQ object
[dpdk.git] / drivers / net / hns3 / hns3_cmd.h
diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
index d70f42e..87d6053 100644 (file)
--- a/drivers/net/hns3/hns3_cmd.h
+++ b/drivers/net/hns3/hns3_cmd.h
@@ -93,12 +93,13 @@ enum hns3_opcode_type {
        HNS3_OPC_QUERY_32_BIT_REG       = 0x0041,
        HNS3_OPC_QUERY_64_BIT_REG       = 0x0042,
 
+       HNS3_OPC_QUERY_DEV_SPECS        = 0x0050,
+
        /* MAC command */
        HNS3_OPC_CONFIG_MAC_MODE        = 0x0301,
        HNS3_OPC_QUERY_LINK_STATUS      = 0x0307,
        HNS3_OPC_CONFIG_MAX_FRM_SIZE    = 0x0308,
        HNS3_OPC_CONFIG_SPEED_DUP       = 0x0309,
-       HNS3_MAC_COMMON_INT_EN          = 0x030E,
 
        /* PFC/Pause commands */
        HNS3_OPC_CFG_MAC_PAUSE_EN       = 0x0701,
@@ -151,10 +152,6 @@ enum hns3_opcode_type {
        HNS3_OPC_RX_COM_THRD_ALLOC      = 0x0904,
        HNS3_OPC_RX_COM_WL_ALLOC        = 0x0905,
 
-       /* SSU module INT commands */
-       HNS3_SSU_ECC_INT_CMD            = 0x0989,
-       HNS3_SSU_COMMON_INT_CMD         = 0x098C,
-
        /* TQP management command */
        HNS3_OPC_SET_TQP_MAP            = 0x0A01,
 
@@ -164,11 +161,6 @@ enum hns3_opcode_type {
        HNS3_OPC_CFG_COM_TQP_QUEUE      = 0x0B20,
        HNS3_OPC_RESET_TQP_QUEUE        = 0x0B22,
 
-       /* PPU module intr commands */
-       HNS3_PPU_MPF_ECC_INT_CMD        = 0x0B40,
-       HNS3_PPU_MPF_OTHER_INT_CMD      = 0x0B41,
-       HNS3_PPU_PF_OTHER_INT_CMD       = 0x0B42,
-
        /* TSO command */
        HNS3_OPC_TSO_GENERIC_CONFIG     = 0x0C01,
        HNS3_OPC_GRO_GENERIC_CONFIG     = 0x0C10,
@@ -214,17 +206,30 @@ enum hns3_opcode_type {
        HNS3_OPC_SFP_GET_SPEED          = 0x7104,
 
        /* Interrupts commands */
-       HNS3_OPC_ADD_RING_TO_VECTOR     = 0x1503,
-       HNS3_OPC_DEL_RING_TO_VECTOR     = 0x1504,
+       HNS3_OPC_ADD_RING_TO_VECTOR     = 0x1503,
+       HNS3_OPC_DEL_RING_TO_VECTOR     = 0x1504,
 
        /* Error INT commands */
-       HNS3_QUERY_MSIX_INT_STS_BD_NUM          = 0x1513,
-       HNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT       = 0x1514,
-       HNS3_QUERY_CLEAR_ALL_PF_MSIX_INT        = 0x1515,
-
-       /* PPP module intr commands */
-       HNS3_PPP_CMD0_INT_CMD                   = 0x2100,
-       HNS3_PPP_CMD1_INT_CMD                   = 0x2101,
+       HNS3_OPC_MAC_COMMON_INT_EN              = 0x030E,
+       HNS3_OPC_TM_SCH_ECC_INT_EN              = 0x0829,
+       HNS3_OPC_SSU_ECC_INT_CMD                = 0x0989,
+       HNS3_OPC_SSU_COMMON_INT_CMD             = 0x098C,
+       HNS3_OPC_PPU_MPF_ECC_INT_CMD            = 0x0B40,
+       HNS3_OPC_PPU_MPF_OTHER_INT_CMD          = 0x0B41,
+       HNS3_OPC_PPU_PF_OTHER_INT_CMD           = 0x0B42,
+       HNS3_OPC_COMMON_ECC_INT_CFG             = 0x1505,
+       HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM       = 0x1510,
+       HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT        = 0x1511,
+       HNS3_OPC_QUERY_CLEAR_PF_RAS_INT         = 0x1512,
+       HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM      = 0x1513,
+       HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT   = 0x1514,
+       HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT    = 0x1515,
+       HNS3_OPC_IGU_EGU_TNL_INT_EN             = 0x1803,
+       HNS3_OPC_IGU_COMMON_INT_EN              = 0x1806,
+       HNS3_OPC_TM_QCN_MEM_INT_CFG             = 0x1A14,
+       HNS3_OPC_PPP_CMD0_INT_CMD               = 0x2100,
+       HNS3_OPC_PPP_CMD1_INT_CMD               = 0x2101,
+       HNS3_OPC_NCSI_INT_EN                    = 0x2401,
 };
 
 #define HNS3_CMD_FLAG_IN       BIT(0)
@@ -234,6 +239,11 @@ enum hns3_opcode_type {
 #define HNS3_CMD_FLAG_NO_INTR  BIT(4)
 #define HNS3_CMD_FLAG_ERR_INTR BIT(5)
 
+#define HNS3_MPF_RAS_INT_MIN_BD_NUM    10
+#define HNS3_PF_RAS_INT_MIN_BD_NUM     4
+#define HNS3_MPF_MSIX_INT_MIN_BD_NUM   10
+#define HNS3_PF_MSIX_INT_MIN_BD_NUM    4
+
 #define HNS3_BUF_SIZE_UNIT     256
 #define HNS3_BUF_MUL_BY                2
 #define HNS3_BUF_DIV_BY                2
@@ -264,9 +274,26 @@ struct hns3_rx_priv_buff_cmd {
 #define HNS3_FW_VERSION_BYTE1_M                GENMASK(15, 8)
 #define HNS3_FW_VERSION_BYTE0_S                0
 #define HNS3_FW_VERSION_BYTE0_M                GENMASK(7, 0)
+
+enum HNS3_CAPS_BITS {
+       HNS3_CAPS_UDP_GSO_B,
+       HNS3_CAPS_ATR_B,
+       HNS3_CAPS_ADQ_B,
+       HNS3_CAPS_PTP_B,
+       HNS3_CAPS_INT_QL_B,
+       HNS3_CAPS_SIMPLE_BD_B,
+       HNS3_CAPS_TX_PUSH_B,
+       HNS3_CAPS_PHY_IMP_B,
+       HNS3_CAPS_TQP_TXRX_INDEP_B,
+       HNS3_CAPS_HW_PAD_B,
+       HNS3_CAPS_STASH_B,
+};
+#define HNS3_QUERY_CAP_LENGTH          3
 struct hns3_query_version_cmd {
        uint32_t firmware;
-       uint32_t firmware_rsv[5];
+       uint32_t hardware;
+       uint32_t rsv;
+       uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
 };
 
 #define HNS3_RX_PRIV_EN_B      15
@@ -349,21 +376,25 @@ struct hns3_func_status_cmd {
        uint8_t rsv[2];
 };
 
-#define HNS3_VEC_NUM_S         0
-#define HNS3_VEC_NUM_M         GENMASK(7, 0)
+#define HNS3_PF_VEC_NUM_S      0
+#define HNS3_PF_VEC_NUM_M      GENMASK(15, 0)
 #define HNS3_MIN_VECTOR_NUM    2 /* one for msi-x, another for IO */
 struct hns3_pf_res_cmd {
        uint16_t tqp_num;
        uint16_t buf_size;
        uint16_t msixcap_localid_ba_nic;
-       uint16_t msixcap_localid_ba_rocee;
-       uint16_t pf_intr_vector_number;
+       uint16_t nic_pf_intr_vector_number;
+       uint16_t roce_pf_intr_vector_number;
        uint16_t pf_own_fun_number;
        uint16_t tx_buf_size;
        uint16_t dv_buf_size;
-       uint32_t rsv[2];
+       uint16_t tqp_num_ext;
+       uint16_t roh_pf_intr_vector_number;
+       uint32_t rsv[1];
 };
 
+#define HNS3_VF_VEC_NUM_S      0
+#define HNS3_VF_VEC_NUM_M      GENMASK(7, 0)
 struct hns3_vf_res_cmd {
        uint16_t tqp_num;
        uint16_t reserved;
@@ -788,6 +819,19 @@ struct hns3_reset_cmd {
        uint8_t rsv[22];
 };
 
+#define HNS3_QUERY_DEV_SPECS_BD_NUM            4
+struct hns3_dev_specs_0_cmd {
+       uint32_t rsv0;
+       uint32_t mac_entry_num;
+       uint32_t mng_entry_num;
+       uint16_t rss_ind_tbl_size;
+       uint16_t rss_key_size;
+       uint16_t intr_ql_max;
+       uint8_t max_non_tso_bd_num;
+       uint8_t rsv1;
+       uint32_t max_tm_rate;
+};
+
 #define HNS3_MAX_TQP_NUM_PER_FUNC      64
 #define HNS3_DEFAULT_TX_BUF            0x4000    /* 16k  bytes */
 #define HNS3_TOTAL_PKT_BUF             0x108000  /* 1.03125M bytes */
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