net/hns3: fix timing of clearing interrupt source

[dpdk.git] / drivers / net / hns3 / hns3_cmd.h

diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
index e4f5aa6..88683df 100644 (file)
--- a/drivers/net/hns3/hns3_cmd.h
+++ b/drivers/net/hns3/hns3_cmd.h
@@ -162,6 +162,9 @@ enum hns3_opcode_type {
        HNS3_OPC_TM_INTERNAL_CNT        = 0x0851,
        HNS3_OPC_TM_INTERNAL_STS_1      = 0x0852,
 
+       HNS3_OPC_TM_PORT_LIMIT_RATE     = 0x0870,
+       HNS3_OPC_TM_TC_LIMIT_RATE       = 0x0871,
+
        /* Mailbox cmd */
        HNS3_OPC_MBX_VF_TO_PF           = 0x2001,
 
@@ -252,6 +255,8 @@ enum hns3_opcode_type {
        HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM      = 0x1513,
        HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT   = 0x1514,
        HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT    = 0x1515,
+       HNS3_OPC_QUERY_ALL_ERR_BD_NUM           = 0x1516,
+       HNS3_OPC_QUERY_ALL_ERR_INFO             = 0x1517,
        HNS3_OPC_IGU_EGU_TNL_INT_EN             = 0x1803,
        HNS3_OPC_IGU_COMMON_INT_EN              = 0x1806,
        HNS3_OPC_TM_QCN_MEM_INT_CFG             = 0x1A14,
@@ -304,22 +309,29 @@ struct hns3_rx_priv_buff_cmd {
 #define HNS3_FW_VERSION_BYTE0_M                GENMASK(7, 0)
 
 enum HNS3_CAPS_BITS {
-       HNS3_CAPS_UDP_GSO_B,
-       HNS3_CAPS_ATR_B,
-       HNS3_CAPS_FD_QUEUE_REGION_B,
+       /*
+        * The following capability index definitions must be the same as those
+        * of the firmware.
+        */
+       HNS3_CAPS_FD_QUEUE_REGION_B = 2,
        HNS3_CAPS_PTP_B,
-       HNS3_CAPS_INT_QL_B,
-       HNS3_CAPS_SIMPLE_BD_B,
-       HNS3_CAPS_TX_PUSH_B,
-       HNS3_CAPS_PHY_IMP_B,
+       HNS3_CAPS_PHY_IMP_B = 7,
        HNS3_CAPS_TQP_TXRX_INDEP_B,
        HNS3_CAPS_HW_PAD_B,
        HNS3_CAPS_STASH_B,
        HNS3_CAPS_UDP_TUNNEL_CSUM_B,
        HNS3_CAPS_RAS_IMP_B,
-       HNS3_CAPS_FEC_B,
-       HNS3_CAPS_PAUSE_B,
-       HNS3_CAPS_RXD_ADV_LAYOUT_B,
+       HNS3_CAPS_RXD_ADV_LAYOUT_B = 15,
+       HNS3_CAPS_TM_B = 17,
+};
+
+/* Capabilities of VF dependent on the PF */
+enum HNS3VF_CAPS_BITS {
+       /*
+        * The following capability index definitions must be the same as those
+        * in kernel side PF.
+        */
+       HNS3VF_CAPS_VLAN_FLT_MOD_B = 0,
 };
 
 enum HNS3_API_CAP_BITS {
@@ -458,8 +470,6 @@ struct hns3_umv_spc_alc_cmd {
 #define HNS3_CFG_RD_LEN_BYTES          16
 #define HNS3_CFG_RD_LEN_UNIT           4
 
-#define HNS3_CFG_VMDQ_S                        0
-#define HNS3_CFG_VMDQ_M                        GENMASK(7, 0)
 #define HNS3_CFG_TC_NUM_S              8
 #define HNS3_CFG_TC_NUM_M              GENMASK(15, 8)
 #define HNS3_CFG_TQP_DESC_N_S          16