net/hns3: fix timing in resetting queues

[dpdk.git] / drivers / net / hns3 / hns3_cmd.h

diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
index 2e23f99..9958fde 100644 (file)
--- a/drivers/net/hns3/hns3_cmd.h
+++ b/drivers/net/hns3/hns3_cmd.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2019 Hisilicon Limited.
+ * Copyright(c) 2018-2021 HiSilicon Limited.
  */
 
 #ifndef _HNS3_CMD_H_
@@ -111,13 +111,22 @@ enum hns3_opcode_type {
 
        HNS3_OPC_QUERY_DEV_SPECS        = 0x0050,
 
+       HNS3_OPC_SSU_DROP_REG           = 0x0065,
+
        /* MAC command */
        HNS3_OPC_CONFIG_MAC_MODE        = 0x0301,
        HNS3_OPC_QUERY_LINK_STATUS      = 0x0307,
        HNS3_OPC_CONFIG_MAX_FRM_SIZE    = 0x0308,
        HNS3_OPC_CONFIG_SPEED_DUP       = 0x0309,
+       HNS3_OPC_QUERY_MAC_TNL_INT      = 0x0310,
+       HNS3_OPC_MAC_TNL_INT_EN         = 0x0311,
+       HNS3_OPC_CLEAR_MAC_TNL_INT      = 0x0312,
        HNS3_OPC_CONFIG_FEC_MODE        = 0x031A,
 
+       /* PTP command */
+       HNS3_OPC_PTP_INT_EN             = 0x0501,
+       HNS3_OPC_CFG_PTP_MODE           = 0x0507,
+
        /* PFC/Pause commands */
        HNS3_OPC_CFG_MAC_PAUSE_EN       = 0x0701,
        HNS3_OPC_CFG_PFC_PAUSE_EN       = 0x0702,
@@ -222,6 +231,8 @@ enum hns3_opcode_type {
 
        /* Firmware stats command */
        HNS3_OPC_FIRMWARE_COMPAT_CFG    = 0x701A,
+       /* Firmware control phy command */
+       HNS3_OPC_PHY_PARAM_CFG          = 0x7025,
 
        /* SFP command */
        HNS3_OPC_GET_SFP_EEPROM         = 0x7100,
@@ -310,6 +321,11 @@ enum HNS3_CAPS_BITS {
        HNS3_CAPS_TQP_TXRX_INDEP_B,
        HNS3_CAPS_HW_PAD_B,
        HNS3_CAPS_STASH_B,
+       HNS3_CAPS_UDP_TUNNEL_CSUM_B,
+       HNS3_CAPS_RAS_IMP_B,
+       HNS3_CAPS_FEC_B,
+       HNS3_CAPS_PAUSE_B,
+       HNS3_CAPS_RXD_ADV_LAYOUT_B,
 };
 
 enum HNS3_API_CAP_BITS {
@@ -659,11 +675,46 @@ enum hns3_promisc_type {
 
 #define HNS3_LINK_EVENT_REPORT_EN_B    0
 #define HNS3_NCSI_ERROR_REPORT_EN_B    1
+#define HNS3_FIRMWARE_PHY_DRIVER_EN_B  2
 struct hns3_firmware_compat_cmd {
        uint32_t compat;
        uint8_t rsv[20];
 };
 
+/* Bitmap flags in supported, advertising and lp_advertising */
+#define HNS3_PHY_LINK_SPEED_10M_HD_BIT         BIT(0)
+#define HNS3_PHY_LINK_SPEED_10M_BIT            BIT(1)
+#define HNS3_PHY_LINK_SPEED_100M_HD_BIT                BIT(2)
+#define HNS3_PHY_LINK_SPEED_100M_BIT           BIT(3)
+#define HNS3_PHY_LINK_MODE_AUTONEG_BIT         BIT(6)
+#define HNS3_PHY_LINK_MODE_PAUSE_BIT           BIT(13)
+#define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT      BIT(14)
+
+#define HNS3_PHY_PARAM_CFG_BD_NUM      2
+struct hns3_phy_params_bd0_cmd {
+       uint32_t speed;
+#define HNS3_PHY_DUPLEX_CFG_B          0
+       uint8_t duplex;
+#define HNS3_PHY_AUTONEG_CFG_B 0
+       uint8_t autoneg;
+       uint8_t eth_tp_mdix;
+       uint8_t eth_tp_mdix_ctrl;
+       uint8_t port;
+       uint8_t transceiver;
+       uint8_t phy_address;
+       uint8_t rsv;
+       uint32_t supported;
+       uint32_t advertising;
+       uint32_t lp_advertising;
+};
+
+struct hns3_phy_params_bd1_cmd {
+       uint8_t master_slave_cfg;
+       uint8_t master_slave_state;
+       uint8_t rsv1[2];
+       uint32_t rsv2[5];
+};
+
 #define HNS3_MAC_TX_EN_B               6
 #define HNS3_MAC_RX_EN_B               7
 #define HNS3_MAC_PAD_TX_B              11
@@ -886,10 +937,16 @@ struct hns3_reset_tqp_queue_cmd {
 
 #define HNS3_CFG_RESET_MAC_B           3
 #define HNS3_CFG_RESET_FUNC_B          7
+#define HNS3_CFG_RESET_RCB_B           1
 struct hns3_reset_cmd {
        uint8_t mac_func_reset;
        uint8_t fun_reset_vfid;
-       uint8_t rsv[22];
+       uint8_t fun_reset_rcb;
+       uint8_t rsv1;
+       uint16_t fun_reset_rcb_vqid_start;
+       uint16_t fun_reset_rcb_vqid_num;
+       uint8_t fun_reset_rcb_return_status;
+       uint8_t rsv2[15];
 };
 
 #define HNS3_QUERY_DEV_SPECS_BD_NUM            4
@@ -905,6 +962,50 @@ struct hns3_dev_specs_0_cmd {
        uint32_t max_tm_rate;
 };
 
+struct hns3_query_rpu_cmd {
+       uint32_t tc_queue_num;
+       uint32_t rsv1[2];
+       uint32_t rpu_rx_pkt_drop_cnt;
+       uint32_t rsv2[2];
+};
+
+#define HNS3_OPC_SSU_DROP_REG_NUM 2
+
+struct hns3_query_ssu_cmd {
+       uint8_t rxtx;
+       uint8_t rsv[3];
+       uint32_t full_drop_cnt;
+       uint32_t part_drop_cnt;
+       uint32_t oq_drop_cnt;
+       uint32_t rev1[2];
+};
+
+#define HNS3_PTP_ENABLE_B               0
+#define HNS3_PTP_TX_ENABLE_B            1
+#define HNS3_PTP_RX_ENABLE_B            2
+
+#define HNS3_PTP_TYPE_S                 0
+#define HNS3_PTP_TYPE_M                (0x3 << HNS3_PTP_TYPE_S)
+
+#define ALL_PTP_V2_TYPE                 0xF
+#define HNS3_PTP_MESSAGE_TYPE_S         0
+#define HNS3_PTP_MESSAGE_TYPE_M        (0xF << HNS3_PTP_MESSAGE_TYPE_S)
+
+#define PTP_TYPE_L2_V2_TYPE             0
+
+struct hns3_ptp_mode_cfg_cmd {
+       uint8_t enable;
+       uint8_t ptp_type;
+       uint8_t v2_message_type_1;
+       uint8_t v2_message_type_0;
+       uint8_t rsv[20];
+};
+
+struct hns3_ptp_int_cmd {
+       uint8_t int_en;
+       uint8_t rsvd[23];
+};
+
 #define HNS3_MAX_TQP_NUM_HIP08_PF      64
 #define HNS3_DEFAULT_TX_BUF            0x4000    /* 16k  bytes */
 #define HNS3_TOTAL_PKT_BUF             0x108000  /* 1.03125M bytes */