#ifndef _HNS3_CMD_H_
#define _HNS3_CMD_H_
+#include <stdint.h>
+
#define HNS3_CMDQ_TX_TIMEOUT 30000
+#define HNS3_CMDQ_CLEAR_WAIT_TIME 200
#define HNS3_CMDQ_RX_INVLD_B 0
#define HNS3_CMDQ_RX_OUTVLD_B 1
#define HNS3_CMD_DESC_ALIGNMENT 4096
-#define HNS3_QUEUE_ID_MASK 0x1ff
#define HNS3_CMD_FLAG_NEXT BIT(2)
struct hns3_hw;
HNS3_CMD_HILINK_ERR = 9,
HNS3_CMD_QUEUE_ILLEGAL = 10,
HNS3_CMD_INVALID = 11,
+ HNS3_CMD_ROH_CHECK_FAIL = 12
};
enum hns3_cmd_status {
HNS3_OPC_QUERY_REG_NUM = 0x0040,
HNS3_OPC_QUERY_32_BIT_REG = 0x0041,
HNS3_OPC_QUERY_64_BIT_REG = 0x0042,
+ HNS3_OPC_DFX_BD_NUM = 0x0043,
+ HNS3_OPC_DFX_BIOS_COMMON_REG = 0x0044,
+ HNS3_OPC_DFX_SSU_REG_0 = 0x0045,
+ HNS3_OPC_DFX_SSU_REG_1 = 0x0046,
+ HNS3_OPC_DFX_IGU_EGU_REG = 0x0047,
+ HNS3_OPC_DFX_RPU_REG_0 = 0x0048,
+ HNS3_OPC_DFX_RPU_REG_1 = 0x0049,
+ HNS3_OPC_DFX_NCSI_REG = 0x004A,
+ HNS3_OPC_DFX_RTC_REG = 0x004B,
+ HNS3_OPC_DFX_PPP_REG = 0x004C,
+ HNS3_OPC_DFX_RCB_REG = 0x004D,
+ HNS3_OPC_DFX_TQP_REG = 0x004E,
+ HNS3_OPC_DFX_SSU_REG_2 = 0x004F,
HNS3_OPC_QUERY_DEV_SPECS = 0x0050,
+ HNS3_OPC_SSU_DROP_REG = 0x0065,
+
/* MAC command */
HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
+ HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310,
+ HNS3_OPC_MAC_TNL_INT_EN = 0x0311,
+ HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312,
+ HNS3_OPC_CONFIG_FEC_MODE = 0x031A,
/* PFC/Pause commands */
HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
HNS3_OPC_QUERY_RX_STATUS = 0x0B13,
HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
+ HNS3_OPC_RESET_TQP_QUEUE_INDEP = 0x0B23,
/* TSO command */
HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
HNS3_OPC_FD_COUNTER_OP = 0x1205,
/* Clear hardware state command */
- HNS3_OPC_CLEAR_HW_STATE = 0x700A,
+ HNS3_OPC_CLEAR_HW_STATE = 0x700B,
+
+ /* Firmware stats command */
+ HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A,
+ /* Firmware control phy command */
+ HNS3_OPC_PHY_PARAM_CFG = 0x7025,
/* SFP command */
+ HNS3_OPC_GET_SFP_EEPROM = 0x7100,
+ HNS3_OPC_GET_SFP_EXIST = 0x7101,
HNS3_OPC_SFP_GET_SPEED = 0x7104,
/* Interrupts commands */
HNS3_CAPS_TQP_TXRX_INDEP_B,
HNS3_CAPS_HW_PAD_B,
HNS3_CAPS_STASH_B,
+ HNS3_CAPS_UDP_TUNNEL_CSUM_B,
+ HNS3_CAPS_RAS_IMP_B,
+ HNS3_CAPS_FEC_B,
+ HNS3_CAPS_PAUSE_B,
+ HNS3_CAPS_RXD_ADV_LAYOUT_B,
+};
+
+enum HNS3_API_CAP_BITS {
+ HNS3_API_CAP_FLEX_RSS_TBL_B,
};
+
#define HNS3_QUERY_CAP_LENGTH 3
struct hns3_query_version_cmd {
uint32_t firmware;
uint32_t hardware;
- uint32_t rsv;
+ uint32_t api_caps;
uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
};
uint16_t pf_own_fun_number;
uint16_t tx_buf_size;
uint16_t dv_buf_size;
- uint16_t tqp_num_ext;
+ /* number of queues that exceed 1024 */
+ uint16_t ext_tqp_num;
uint16_t roh_pf_intr_vector_number;
uint32_t rsv[1];
};
HNS3_BROADCAST = 3,
};
+#define HNS3_LINK_EVENT_REPORT_EN_B 0
+#define HNS3_NCSI_ERROR_REPORT_EN_B 1
+#define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2
+struct hns3_firmware_compat_cmd {
+ uint32_t compat;
+ uint8_t rsv[20];
+};
+
+/* Bitmap flags in supported, advertising and lp_advertising */
+#define HNS3_PHY_LINK_SPEED_10M_HD_BIT BIT(0)
+#define HNS3_PHY_LINK_SPEED_10M_BIT BIT(1)
+#define HNS3_PHY_LINK_SPEED_100M_HD_BIT BIT(2)
+#define HNS3_PHY_LINK_SPEED_100M_BIT BIT(3)
+#define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6)
+#define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13)
+#define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14)
+
+#define HNS3_PHY_PARAM_CFG_BD_NUM 2
+struct hns3_phy_params_bd0_cmd {
+ uint32_t speed;
+#define HNS3_PHY_DUPLEX_CFG_B 0
+ uint8_t duplex;
+#define HNS3_PHY_AUTONEG_CFG_B 0
+ uint8_t autoneg;
+ uint8_t eth_tp_mdix;
+ uint8_t eth_tp_mdix_ctrl;
+ uint8_t port;
+ uint8_t transceiver;
+ uint8_t phy_address;
+ uint8_t rsv;
+ uint32_t supported;
+ uint32_t advertising;
+ uint32_t lp_advertising;
+};
+
+struct hns3_phy_params_bd1_cmd {
+ uint8_t master_slave_cfg;
+ uint8_t master_slave_state;
+ uint8_t rsv1[2];
+ uint32_t rsv2[5];
+};
+
#define HNS3_MAC_TX_EN_B 6
#define HNS3_MAC_RX_EN_B 7
#define HNS3_MAC_PAD_TX_B 11
uint8_t rsv[22];
};
-#define HNS3_RING_ID_MASK GENMASK(9, 0)
#define HNS3_TQP_ENABLE_B 0
#define HNS3_MAC_CFG_AN_EN_B 0
uint8_t rsv[20];
};
+#define HNS3_MAC_CFG_FEC_AUTO_EN_B 0
+#define HNS3_MAC_CFG_FEC_MODE_S 1
+#define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
+#define HNS3_MAC_FEC_OFF 0
+#define HNS3_MAC_FEC_BASER 1
+#define HNS3_MAC_FEC_RS 2
+
+#define HNS3_SFP_INFO_BD0_LEN 20UL
+#define HNS3_SFP_INFO_BDX_LEN 24UL
+
+struct hns3_sfp_info_bd0_cmd {
+ uint16_t offset;
+ uint16_t read_len;
+ uint8_t data[HNS3_SFP_INFO_BD0_LEN];
+};
+
+struct hns3_sfp_type {
+ uint8_t type;
+ uint8_t ext_type;
+};
+
struct hns3_sfp_speed_cmd {
uint32_t sfp_speed;
- uint32_t rsv[5];
+ uint8_t query_type; /* 0: sfp speed, 1: active fec */
+ uint8_t active_fec; /* current FEC mode */
+ uint16_t rsv1;
+ uint32_t rsv2[4];
+};
+
+/* Configure FEC mode, opcode:0x031A */
+struct hns3_config_fec_cmd {
+ uint8_t fec_mode;
+ uint8_t rsv[23];
};
#define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
#define HNS3_TQP_ID_M GENMASK(12, 2)
#define HNS3_INT_GL_IDX_S 13
#define HNS3_INT_GL_IDX_M GENMASK(14, 13)
+#define HNS3_TQP_INT_ID_L_S 0
+#define HNS3_TQP_INT_ID_L_M GENMASK(7, 0)
+#define HNS3_TQP_INT_ID_H_S 8
+#define HNS3_TQP_INT_ID_H_M GENMASK(15, 8)
struct hns3_ctrl_vector_chain_cmd {
- uint8_t int_vector_id;
+ uint8_t int_vector_id; /* the low order of the interrupt id */
uint8_t int_cause_num;
uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
uint8_t vfid;
- uint8_t rsv;
+ uint8_t int_vector_id_h; /* the high order of the interrupt id */
};
struct hns3_config_max_frm_size_cmd {
uint16_t tqp_id;
uint8_t reset_req;
uint8_t ready_to_reset;
- uint8_t rsv[20];
+ uint8_t queue_direction;
+ uint8_t rsv[19];
};
#define HNS3_CFG_RESET_MAC_B 3
uint32_t max_tm_rate;
};
-#define HNS3_MAX_TQP_NUM_PER_FUNC 64
+struct hns3_query_rpu_cmd {
+ uint32_t tc_queue_num;
+ uint32_t rsv1[2];
+ uint32_t rpu_rx_pkt_drop_cnt;
+ uint32_t rsv2[2];
+};
+
+#define HNS3_OPC_SSU_DROP_REG_NUM 2
+
+struct hns3_query_ssu_cmd {
+ uint8_t rxtx;
+ uint8_t rsv[3];
+ uint32_t full_drop_cnt;
+ uint32_t part_drop_cnt;
+ uint32_t oq_drop_cnt;
+ uint32_t rev1[2];
+};
+
+#define HNS3_MAX_TQP_NUM_HIP08_PF 64
#define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
#define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
#define HNS3_DEFAULT_DV 0xA000 /* 40k byte */
git.droids-corp.org / dpdk.git / blobdiff