*/
HNS3_CAPS_FD_QUEUE_REGION_B = 2,
HNS3_CAPS_PTP_B,
+ HNS3_CAPS_TX_PUSH_B = 6,
HNS3_CAPS_PHY_IMP_B = 7,
HNS3_CAPS_TQP_TXRX_INDEP_B,
HNS3_CAPS_HW_PAD_B,
HNS3_CAPS_TM_B = 17,
};
+/* Capabilities of VF dependent on the PF */
+enum HNS3VF_CAPS_BITS {
+ /*
+ * The following capability index definitions must be the same as those
+ * in kernel side PF.
+ */
+ HNS3VF_CAPS_VLAN_FLT_MOD_B = 0,
+};
+
enum HNS3_API_CAP_BITS {
HNS3_API_CAP_FLEX_RSS_TBL_B,
};
#define HNS3_RSS_HASH_KEY_OFFSET_B 4
-#define HNS3_RSS_CFG_TBL_SIZE 16
#define HNS3_RSS_HASH_KEY_NUM 16
/* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
struct hns3_rss_generic_config_cmd {
HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
};
-#define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
+#define HNS3_MC_MAC_VLAN_OPS_DESC_NUM 3
+#define HNS3_UC_MAC_VLAN_OPS_DESC_NUM 1
#define HNS3_MAC_VLAN_BIT0_EN_B 0
#define HNS3_MAC_VLAN_BIT1_EN_B 1