goto cfg_err;
}
- /* When RSS is not configured, redirect the packet queue 0 */
if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
rss_conf = conf->rx_adv_conf.rss_conf;
- hw->rss_dis_flag = false;
ret = hns3_dev_rss_hash_update(dev, &rss_conf);
if (ret)
goto cfg_err;
hw->mac.media_type = cfg.media_type;
hw->rss_size_max = cfg.rss_size_max;
- hw->rss_dis_flag = false;
memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
hw->mac.phy_addr = cfg.phy_addr;
hw->dcb_info.num_pg = 1;
struct hns3_adapter *hns = eth_dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
- if (!hns3_is_reset_pending(hns))
+ if (!hns3_is_reset_pending(hns)) {
hns3_update_linkstatus_and_event(hw, true);
- else
+ hns3_update_hw_stats(hw);
+ } else {
hns3_warn(hw, "Cancel the query when reset is pending");
+ }
rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
}
struct hns3_hw *hw = &hns->hw;
int ret;
+ /*
+ * All queue-related HW operations must be performed after the TCAM
+ * table is configured.
+ */
ret = hns3_map_tqp(hw);
if (ret) {
PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
goto err_cmd_init;
}
- /* Hardware statistics of imissed registers cleared. */
- ret = hns3_update_imissed_stats(hw, true);
- if (ret) {
- hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
- goto err_cmd_init;
- }
-
hns3_config_all_msix_error(hw, true);
ret = rte_intr_callback_register(pci_dev->intr_handle,
goto err_get_config;
}
- ret = hns3_tqp_stats_init(hw);
+ ret = hns3_stats_init(hw);
if (ret)
goto err_get_config;
err_fdir:
hns3_uninit_umv_space(hw);
err_init_hw:
- hns3_tqp_stats_uninit(hw);
+ hns3_stats_uninit(hw);
err_get_config:
hns3_pf_disable_irq0(hw);
rte_intr_disable(pci_dev->intr_handle);
hns3_flow_uninit(eth_dev);
hns3_fdir_filter_uninit(hns);
hns3_uninit_umv_space(hw);
- hns3_tqp_stats_uninit(hw);
+ hns3_stats_uninit(hw);
hns3_config_mac_tnl_int(hw, false);
hns3_pf_disable_irq0(hw);
rte_intr_disable(pci_dev->intr_handle);
return hns3_get_autoneg_fc_mode(hw);
}
-static int
+int
hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
return ret;
}
- ret = hns3_reset_all_tqps(hns);
+ ret = hns3_init_hardware(hns);
if (ret) {
- hns3_err(hw, "Failed to reset all queues: %d", ret);
+ hns3_err(hw, "Failed to init hardware: %d", ret);
return ret;
}
- ret = hns3_init_hardware(hns);
+ ret = hns3_reset_all_tqps(hns);
if (ret) {
- hns3_err(hw, "Failed to init hardware: %d", ret);
+ hns3_err(hw, "Failed to reset all queues: %d", ret);
return ret;
}
.timesync_adjust_time = hns3_timesync_adjust_time,
.timesync_read_time = hns3_timesync_read_time,
.timesync_write_time = hns3_timesync_write_time,
+ .eth_dev_priv_dump = hns3_eth_dev_priv_dump,
};
static const struct hns3_reset_ops hns3_reset_ops = {