#include <rte_alarm.h>
#include <rte_bus_pci.h>
#include <ethdev_pci.h>
-#include <rte_pci.h>
#include "hns3_ethdev.h"
#include "hns3_common.h"
return ret;
}
-static void
-hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
- struct hns3_rx_vtag_cfg *vcfg)
-{
- struct hns3_pf *pf = &hns->pf;
- memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
-}
-
-static void
-hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
- struct hns3_tx_vtag_cfg *vcfg)
-{
- struct hns3_pf *pf = &hns->pf;
- memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
-}
-
static int
hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
{
return ret;
}
- hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
+ memcpy(&hns->pf.vtag_config.rx_vcfg, &rxvlan_cfg,
+ sizeof(struct hns3_rx_vtag_cfg));
return ret;
}
return ret;
}
- hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
+ memcpy(&hns->pf.vtag_config.tx_vcfg, &txvlan_cfg,
+ sizeof(struct hns3_tx_vtag_cfg));
+
return ret;
}
if (ret)
return ret;
- hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
+ memcpy(&hns->pf.vtag_config.rx_vcfg, &rx_vlan_cfg,
+ sizeof(struct hns3_rx_vtag_cfg));
+
return ret;
}
goto cfg_err;
}
- /* When RSS is not configured, redirect the packet queue 0 */
if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
rss_conf = conf->rx_adv_conf.rss_conf;
- hw->rss_dis_flag = false;
ret = hns3_dev_rss_hash_update(dev, &rss_conf);
if (ret)
goto cfg_err;
hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
{
struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
- uint16_t original_mps = hns->pf.mps;
int err;
int ret;
return ret;
}
- hns->pf.mps = mps;
ret = hns3_buffer_alloc(hw);
if (ret) {
hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
goto rollback;
}
+ hns->pf.mps = mps;
+
return 0;
rollback:
- err = hns3_set_mac_mtu(hw, original_mps);
- if (err) {
+ err = hns3_set_mac_mtu(hw, hns->pf.mps);
+ if (err)
hns3_err(hw, "fail to rollback MTU, err = %d", err);
- return ret;
- }
- hns->pf.mps = original_mps;
return ret;
}
/* get the configuration */
cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
- cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
- HNS3_CFG_TQP_DESC_N_M,
- HNS3_CFG_TQP_DESC_N_S);
cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
HNS3_CFG_PHY_ADDR_M,
cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
HNS3_CFG_MEDIA_TP_M,
HNS3_CFG_MEDIA_TP_S);
- cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
- HNS3_CFG_RX_BUF_LEN_M,
- HNS3_CFG_RX_BUF_LEN_S);
/* get mac address */
mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
struct hns3_pf *pf = &hns->pf;
struct rte_eth_dev *eth_dev;
uint16_t device_id;
- uint8_t revision;
int ret;
eth_dev = &rte_eth_devices[hw->data->port_id];
device_id == HNS3_DEV_ID_200G_RDMA)
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
- /* Get PCI revision id */
- ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
- HNS3_PCI_REVISION_ID);
- if (ret != HNS3_PCI_REVISION_ID_LEN) {
- PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
- ret);
- return -EIO;
- }
- hw->revision = revision;
+ ret = hns3_get_pci_revision_id(hw, &hw->revision);
+ if (ret)
+ return ret;
- if (revision < PCI_REVISION_ID_HIP09_A) {
+ ret = hns3_query_mac_stats_reg_num(hw);
+ if (ret)
+ return ret;
+
+ if (hw->revision < PCI_REVISION_ID_HIP09_A) {
hns3_set_default_dev_specifications(hw);
hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
hw->mac.media_type = cfg.media_type;
hw->rss_size_max = cfg.rss_size_max;
- hw->rss_dis_flag = false;
memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
hw->mac.phy_addr = cfg.phy_addr;
- hw->num_tx_desc = cfg.tqp_desc_num;
- hw->num_rx_desc = cfg.tqp_desc_num;
hw->dcb_info.num_pg = 1;
hw->dcb_info.hw_pfc_map = 0;
struct hns3_adapter *hns = eth_dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
- if (!hns3_is_reset_pending(hns))
+ if (!hns3_is_reset_pending(hns)) {
hns3_update_linkstatus_and_event(hw, true);
- else
+ hns3_update_hw_stats(hw);
+ } else {
hns3_warn(hw, "Cancel the query when reset is pending");
+ }
rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
}
struct hns3_hw *hw = &hns->hw;
int ret;
+ /*
+ * All queue-related HW operations must be performed after the TCAM
+ * table is configured.
+ */
ret = hns3_map_tqp(hw);
if (ret) {
PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
goto err_cmd_init;
}
- /* Hardware statistics of imissed registers cleared. */
- ret = hns3_update_imissed_stats(hw, true);
- if (ret) {
- hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
- goto err_cmd_init;
- }
-
hns3_config_all_msix_error(hw, true);
ret = rte_intr_callback_register(pci_dev->intr_handle,
goto err_get_config;
}
- ret = hns3_tqp_stats_init(hw);
+ ret = hns3_stats_init(hw);
if (ret)
goto err_get_config;
err_fdir:
hns3_uninit_umv_space(hw);
err_init_hw:
- hns3_tqp_stats_uninit(hw);
+ hns3_stats_uninit(hw);
err_get_config:
hns3_pf_disable_irq0(hw);
rte_intr_disable(pci_dev->intr_handle);
hns3_flow_uninit(eth_dev);
hns3_fdir_filter_uninit(hns);
hns3_uninit_umv_space(hw);
- hns3_tqp_stats_uninit(hw);
+ hns3_stats_uninit(hw);
hns3_config_mac_tnl_int(hw, false);
hns3_pf_disable_irq0(hw);
rte_intr_disable(pci_dev->intr_handle);
return hns3_get_autoneg_fc_mode(hw);
}
-static int
+int
hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
return ret;
}
- ret = hns3_reset_all_tqps(hns);
+ ret = hns3_init_hardware(hns);
if (ret) {
- hns3_err(hw, "Failed to reset all queues: %d", ret);
+ hns3_err(hw, "Failed to init hardware: %d", ret);
return ret;
}
- ret = hns3_init_hardware(hns);
+ ret = hns3_reset_all_tqps(hns);
if (ret) {
- hns3_err(hw, "Failed to init hardware: %d", ret);
+ hns3_err(hw, "Failed to reset all queues: %d", ret);
return ret;
}
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
struct hns3_pf *pf = &hns->pf;
-
struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
uint32_t cur_capa;
uint32_t num = FEC_CAPA_NUM;
.timesync_adjust_time = hns3_timesync_adjust_time,
.timesync_read_time = hns3_timesync_read_time,
.timesync_write_time = hns3_timesync_write_time,
+ .eth_dev_priv_dump = hns3_eth_dev_priv_dump,
};
static const struct hns3_reset_ops hns3_reset_ops = {
git.droids-corp.org / dpdk.git / blobdiff