hns3_pf_disable_irq0(hw);
event_cause = hns3_check_event_cause(hns, &clearval);
-
/* vector 0 interrupt is shared with reset and mailbox source events. */
if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
hns3_warn(hw, "Received err interrupt");
for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
priv = &buf_alloc->priv_buf[i];
mask = BIT((uint8_t)i);
-
- if (hw->hw_tc_map & mask &&
- hw->dcb_info.hw_pfc_map & mask) {
+ if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
/* Reduce the number of pfc TC with private buffer */
priv->wl.low = 0;
priv->enable = 0;
for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
priv = &buf_alloc->priv_buf[i];
-
priv->enable = 0;
priv->wl.low = 0;
priv->wl.high = 0;
/* Enable interrupt of all rx queues before enabling queues */
hns3_dev_all_rx_queue_intr_enable(hw, true);
+ /*
+ * Enable state of each rxq and txq will be recovered after
+ * reset, so we need to restore them before enable all tqps;
+ */
+ hns3_restore_tqp_enable_state(hw);
/*
* When finished the initialization, enable queues to receive
* and transmit packets.