#include <rte_alarm.h>
#include <rte_bus_pci.h>
#include <ethdev_pci.h>
-#include <rte_pci.h>
#include "hns3_ethdev.h"
#include "hns3_common.h"
return ret;
}
-static bool
-hns3_is_1588_event_type(uint32_t event_type)
-{
- return (event_type == HNS3_VECTOR0_EVENT_PTP);
-}
-
static void
hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
{
if (event_type == HNS3_VECTOR0_EVENT_RST ||
- hns3_is_1588_event_type(event_type))
+ event_type == HNS3_VECTOR0_EVENT_PTP)
hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
else if (event_type == HNS3_VECTOR0_EVENT_MBX)
hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
vcfg->vlan2_vlan_prionly ? 1 : 0);
- /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
+ /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */
hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
vcfg->strip_tag1_discard_en ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
return ret;
}
-static void
-hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
- struct hns3_rx_vtag_cfg *vcfg)
-{
- struct hns3_pf *pf = &hns->pf;
- memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
-}
-
-static void
-hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
- struct hns3_tx_vtag_cfg *vcfg)
-{
- struct hns3_pf *pf = &hns->pf;
- memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
-}
-
static int
hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
{
return ret;
}
- hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
+ memcpy(&hns->pf.vtag_config.rx_vcfg, &rxvlan_cfg,
+ sizeof(struct hns3_rx_vtag_cfg));
return ret;
}
vcfg->insert_tag2_en ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
- /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
+ /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */
hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
vcfg->tag_shift_mode_en ? 1 : 0);
return ret;
}
- hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
+ memcpy(&hns->pf.vtag_config.tx_vcfg, &txvlan_cfg,
+ sizeof(struct hns3_tx_vtag_cfg));
+
return ret;
}
if (ret)
return ret;
- hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
+ memcpy(&hns->pf.vtag_config.rx_vcfg, &rx_vlan_cfg,
+ sizeof(struct hns3_rx_vtag_cfg));
+
return ret;
}
return ret;
/*
* Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
- * need be processed by PMD driver.
+ * need be processed by PMD.
*/
if (pvid_en_state_change &&
hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
{
struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
- uint16_t original_mps = hns->pf.mps;
int err;
int ret;
return ret;
}
- hns->pf.mps = mps;
ret = hns3_buffer_alloc(hw);
if (ret) {
hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
goto rollback;
}
+ hns->pf.mps = mps;
+
return 0;
rollback:
- err = hns3_set_mac_mtu(hw, original_mps);
- if (err) {
+ err = hns3_set_mac_mtu(hw, hns->pf.mps);
+ if (err)
hns3_err(hw, "fail to rollback MTU, err = %d", err);
- return ret;
- }
- hns->pf.mps = original_mps;
return ret;
}
/* get the configuration */
cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
- cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
- HNS3_CFG_TQP_DESC_N_M,
- HNS3_CFG_TQP_DESC_N_S);
cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
HNS3_CFG_PHY_ADDR_M,
cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
HNS3_CFG_MEDIA_TP_M,
HNS3_CFG_MEDIA_TP_S);
- cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
- HNS3_CFG_RX_BUF_LEN_M,
- HNS3_CFG_RX_BUF_LEN_S);
/* get mac address */
mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
* Field ext_rss_size_max obtained from firmware will be more flexible
* for future changes and expansions, which is an exponent of 2, instead
* of reading out directly. If this field is not zero, hns3 PF PMD
- * driver uses it as rss_size_max under one TC. Device, whose revision
+ * uses it as rss_size_max under one TC. Device, whose revision
* id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
* maximum number of queues supported under a TC through this field.
*/
struct hns3_pf *pf = &hns->pf;
struct rte_eth_dev *eth_dev;
uint16_t device_id;
- uint8_t revision;
int ret;
eth_dev = &rte_eth_devices[hw->data->port_id];
device_id == HNS3_DEV_ID_200G_RDMA)
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
- /* Get PCI revision id */
- ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
- HNS3_PCI_REVISION_ID);
- if (ret != HNS3_PCI_REVISION_ID_LEN) {
- PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
- ret);
- return -EIO;
- }
- hw->revision = revision;
+ ret = hns3_get_pci_revision_id(hw, &hw->revision);
+ if (ret)
+ return ret;
+
+ ret = hns3_query_mac_stats_reg_num(hw);
+ if (ret)
+ return ret;
- if (revision < PCI_REVISION_ID_HIP09_A) {
+ if (hw->revision < PCI_REVISION_ID_HIP09_A) {
hns3_set_default_dev_specifications(hw);
hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
hw->rss_dis_flag = false;
memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
hw->mac.phy_addr = cfg.phy_addr;
- hw->num_tx_desc = cfg.tqp_desc_num;
- hw->num_rx_desc = cfg.tqp_desc_num;
hw->dcb_info.num_pg = 1;
hw->dcb_info.hw_pfc_map = 0;
* hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
* @hw: pointer to struct hns3_hw
* @buf_alloc: pointer to buffer calculation data
- * @return: 0: calculate sucessful, negative: fail
+ * @return: 0: calculate successful, negative: fail
*/
static int
hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
struct hns3_hw *hw = &hns->hw;
int ret;
+ /*
+ * All queue-related HW operations must be performed after the TCAM
+ * table is configured.
+ */
ret = hns3_map_tqp(hw);
if (ret) {
PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
}
/*
- * Validity of supported_speed for firber and copper media type can be
+ * Validity of supported_speed for fiber and copper media type can be
* guaranteed by the following policy:
* Copper:
* Although the initialization of the phy in the firmware may not be
* completed, the firmware can guarantees that the supported_speed is
* an valid value.
* Firber:
- * If the version of firmware supports the acitive query way of the
+ * If the version of firmware supports the active query way of the
* HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
* through it. If unsupported, use the SFP's speed as the value of the
* supported_speed.
return 0;
}
-static inline uint32_t
+static uint32_t
hns3_get_link_speed(uint32_t link_speeds)
{
uint32_t speed = RTE_ETH_SPEED_NUM_NONE;
/*
* Flow control auto-negotiation is not supported for fiber and
- * backpalne media type.
+ * backplane media type.
*/
case HNS3_MEDIA_TYPE_FIBER:
case HNS3_MEDIA_TYPE_BACKPLANE:
return ret;
}
- ret = hns3_reset_all_tqps(hns);
+ ret = hns3_init_hardware(hns);
if (ret) {
- hns3_err(hw, "Failed to reset all queues: %d", ret);
+ hns3_err(hw, "Failed to init hardware: %d", ret);
return ret;
}
- ret = hns3_init_hardware(hns);
+ ret = hns3_reset_all_tqps(hns);
if (ret) {
- hns3_err(hw, "Failed to init hardware: %d", ret);
+ hns3_err(hw, "Failed to reset all queues: %d", ret);
return ret;
}
}
/*
- * FEC mode order defined in hns3 hardware is inconsistend with
+ * FEC mode order defined in hns3 hardware is inconsistent with
* that defined in the ethdev library. So the sequence needs
* to be converted.
*/
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
struct hns3_pf *pf = &hns->pf;
-
struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
uint32_t cur_capa;
uint32_t num = FEC_CAPA_NUM;
if (ret < 0)
return ret;
- /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
+ /* HNS3 PMD only support one bit set mode, e.g. 0x1, 0x4 */
if (!is_fec_mode_one_bit_set(mode)) {
hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
"FEC mode should be only one bit set", mode);
hns3_dev_init(struct rte_eth_dev *eth_dev)
{
struct hns3_adapter *hns = eth_dev->data->dev_private;
- char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
- struct rte_ether_addr *eth_addr;
struct hns3_hw *hw = &hns->hw;
int ret;
goto err_init_pf;
}
- /* Allocate memory for storing MAC addresses */
- eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
- sizeof(struct rte_ether_addr) *
- HNS3_UC_MACADDR_NUM, 0);
- if (eth_dev->data->mac_addrs == NULL) {
- PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
- "to store MAC addresses",
- sizeof(struct rte_ether_addr) *
- HNS3_UC_MACADDR_NUM);
- ret = -ENOMEM;
- goto err_rte_zmalloc;
- }
-
- eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
- if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
- rte_eth_random_addr(hw->mac.mac_addr);
- hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
- (struct rte_ether_addr *)hw->mac.mac_addr);
- hns3_warn(hw, "default mac_addr from firmware is an invalid "
- "unicast address, using random MAC address %s",
- mac_str);
- }
- rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
- ð_dev->data->mac_addrs[0]);
+ ret = hns3_init_mac_addrs(eth_dev);
+ if (ret != 0)
+ goto err_init_mac_addrs;
hw->adapter_state = HNS3_NIC_INITIALIZED;
hns3_info(hw, "hns3 dev initialization successful!");
return 0;
-err_rte_zmalloc:
+err_init_mac_addrs:
hns3_uninit_pf(eth_dev);
err_init_pf: