net/hns3: get device capability in primary process

[dpdk.git] / drivers / net / hns3 / hns3_ethdev.c

diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
index 39136d2..4afee5d 100644 (file)
--- a/drivers/net/hns3/hns3_ethdev.c
+++ b/drivers/net/hns3/hns3_ethdev.c
@@ -905,6 +905,8 @@ hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 {
        struct hns3_adapter *hns = dev->data->dev_private;
        struct hns3_hw *hw = &hns->hw;
+       bool pvid_en_state_change;
+       uint16_t pvid_state;
        int ret;
 
        if (pvid > RTE_ETHER_MAX_VLAN_ID) {
@@ -913,10 +915,27 @@ hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
                return -EINVAL;
        }
 
+       /*
+        * If PVID configuration state change, should refresh the PVID
+        * configuration state in struct hns3_tx_queue/hns3_rx_queue.
+        */
+       pvid_state = hw->port_base_vlan_cfg.state;
+       if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
+           (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
+               pvid_en_state_change = false;
+       else
+               pvid_en_state_change = true;
+
        rte_spinlock_lock(&hw->lock);
        ret = hns3_vlan_pvid_configure(hns, pvid, on);
        rte_spinlock_unlock(&hw->lock);
-       return ret;
+       if (ret)
+               return ret;
+
+       if (pvid_en_state_change)
+               hns3_update_all_queues_pvid_state(hw);
+
+       return 0;
 }
 
 static void
@@ -2454,14 +2473,13 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
                                 DEV_TX_OFFLOAD_TCP_CKSUM |
                                 DEV_TX_OFFLOAD_UDP_CKSUM |
                                 DEV_TX_OFFLOAD_SCTP_CKSUM |
-                                DEV_TX_OFFLOAD_VLAN_INSERT |
-                                DEV_TX_OFFLOAD_QINQ_INSERT |
                                 DEV_TX_OFFLOAD_MULTI_SEGS |
                                 DEV_TX_OFFLOAD_TCP_TSO |
                                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
                                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
                                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
-                                info->tx_queue_offload_capa);
+                                info->tx_queue_offload_capa |
+                                hns3_txvlan_cap_get(hw));
 
        info->rx_desc_lim = (struct rte_eth_desc_lim) {
                .nb_max = HNS3_MAX_RING_DESC,
@@ -2776,6 +2794,36 @@ hns3_parse_speed(int speed_cmd, uint32_t *speed)
        return 0;
 }
 
+static int
+hns3_get_capability(struct hns3_hw *hw)
+{
+       struct rte_pci_device *pci_dev;
+       struct rte_eth_dev *eth_dev;
+       uint16_t device_id;
+       uint8_t revision;
+       int ret;
+
+       eth_dev = &rte_eth_devices[hw->data->port_id];
+       pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
+       device_id = pci_dev->id.device_id;
+
+       if (device_id == HNS3_DEV_ID_25GE_RDMA ||
+           device_id == HNS3_DEV_ID_50GE_RDMA ||
+           device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
+               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
+
+       /* Get PCI revision id */
+       ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
+                                 HNS3_PCI_REVISION_ID);
+       if (ret != HNS3_PCI_REVISION_ID_LEN) {
+               PMD_INIT_LOG(ERR, "failed to read pci revision id: %d", ret);
+               return -EIO;
+       }
+       hw->revision = revision;
+
+       return 0;
+}
+
 static int
 hns3_get_board_configuration(struct hns3_hw *hw)
 {
@@ -2851,6 +2899,13 @@ hns3_get_configuration(struct hns3_hw *hw)
                return ret;
        }
 
+       /* Get device capability */
+       ret = hns3_get_capability(hw);
+       if (ret) {
+               PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
+               return ret;
+       }
+
        /* Get pf resource */
        ret = hns3_query_pf_resource(hw);
        if (ret) {
@@ -5345,26 +5400,12 @@ static const struct hns3_reset_ops hns3_reset_ops = {
 static int
 hns3_dev_init(struct rte_eth_dev *eth_dev)
 {
-       struct rte_device *dev = eth_dev->device;
-       struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
        struct hns3_adapter *hns = eth_dev->data->dev_private;
        struct hns3_hw *hw = &hns->hw;
-       uint16_t device_id = pci_dev->id.device_id;
-       uint8_t revision;
        int ret;
 
        PMD_INIT_FUNC_TRACE();
 
-       /* Get PCI revision id */
-       ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
-                                 HNS3_PCI_REVISION_ID);
-       if (ret != HNS3_PCI_REVISION_ID_LEN) {
-               PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
-                            ret);
-               return -EIO;
-       }
-       hw->revision = revision;
-
        eth_dev->process_private = (struct hns3_process_private *)
            rte_zmalloc_socket("hns3_filter_list",
                               sizeof(struct hns3_process_private),
@@ -5386,12 +5427,6 @@ hns3_dev_init(struct rte_eth_dev *eth_dev)
 
        hns3_mp_init_primary();
        hw->adapter_state = HNS3_NIC_UNINITIALIZED;
-
-       if (device_id == HNS3_DEV_ID_25GE_RDMA ||
-           device_id == HNS3_DEV_ID_50GE_RDMA ||
-           device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
-               hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
-
        hns->is_vf = false;
        hw->data = eth_dev->data;