net/iavf: disable simple XOR RSS hash function

[dpdk.git] / drivers / net / hns3 / hns3_ethdev.c

diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
index b9868de..81e7730 100644 (file)
--- a/drivers/net/hns3/hns3_ethdev.c
+++ b/drivers/net/hns3/hns3_ethdev.c
@@ -2450,7 +2450,7 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
        info->max_rx_queues = queue_num;
        info->max_tx_queues = hw->tqps_num;
        info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
-       info->min_rx_bufsize = hw->rx_buf_len;
+       info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
        info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
        info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
        info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
@@ -2560,6 +2560,7 @@ hns3_dev_link_update(struct rte_eth_dev *eth_dev,
        case ETH_SPEED_NUM_40G:
        case ETH_SPEED_NUM_50G:
        case ETH_SPEED_NUM_100G:
+       case ETH_SPEED_NUM_200G:
                new_link.link_speed = mac->link_speed;
                break;
        default:
@@ -2789,6 +2790,9 @@ hns3_parse_speed(int speed_cmd, uint32_t *speed)
        case HNS3_CFG_SPEED_100G:
                *speed = ETH_SPEED_NUM_100G;
                break;
+       case HNS3_CFG_SPEED_200G:
+               *speed = ETH_SPEED_NUM_200G;
+               break;
        default:
                return -EINVAL;
        }
@@ -2811,7 +2815,8 @@ hns3_get_capability(struct hns3_hw *hw)
 
        if (device_id == HNS3_DEV_ID_25GE_RDMA ||
            device_id == HNS3_DEV_ID_50GE_RDMA ||
-           device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
+           device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
+           device_id == HNS3_DEV_ID_200G_RDMA)
                hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
 
        /* Get PCI revision id */
@@ -2823,6 +2828,9 @@ hns3_get_capability(struct hns3_hw *hw)
        }
        hw->revision = revision;
 
+       if (revision >= PCI_REVISION_ID_HIP09_A)
+               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1);
+
        return 0;
 }
 
@@ -2840,7 +2848,8 @@ hns3_get_board_configuration(struct hns3_hw *hw)
                return ret;
        }
 
-       if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
+       if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
+           !hns3_dev_copper_supported(hw)) {
                PMD_INIT_LOG(ERR, "media type is copper, not supported.");
                return -EOPNOTSUPP;
        }
@@ -2848,7 +2857,6 @@ hns3_get_board_configuration(struct hns3_hw *hw)
        hw->mac.media_type = cfg.media_type;
        hw->rss_size_max = cfg.rss_size_max;
        hw->rss_dis_flag = false;
-       hw->rx_buf_len = cfg.rx_buf_len;
        memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
        hw->mac.phy_addr = cfg.phy_addr;
        hw->mac.default_addr_setted = false;
@@ -3024,6 +3032,10 @@ hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
                hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
                               HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
                break;
+       case ETH_SPEED_NUM_200G:
+               hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
+                              HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
+               break;
        default:
                PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
                return -EINVAL;
@@ -4172,7 +4184,15 @@ hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
        hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
        hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
        hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
-       hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
+
+       /*
+        * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
+        * when receiving frames. Otherwise, CRC will be stripped.
+        */
+       if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
+               hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
+       else
+               hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
        hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
        hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
        hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
@@ -5449,12 +5469,25 @@ hns3_dev_init(struct rte_eth_dev *eth_dev)
        hns3_set_rxtx_function(eth_dev);
        eth_dev->dev_ops = &hns3_eth_dev_ops;
        if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
-               hns3_mp_init_secondary();
+               ret = hns3_mp_init_secondary();
+               if (ret) {
+                       PMD_INIT_LOG(ERR, "Failed to init for secondary "
+                                    "process, ret = %d", ret);
+                       goto err_mp_init_secondary;
+               }
+
                hw->secondary_cnt++;
                return 0;
        }
 
-       hns3_mp_init_primary();
+       ret = hns3_mp_init_primary();
+       if (ret) {
+               PMD_INIT_LOG(ERR,
+                            "Failed to init for primary process, ret = %d",
+                            ret);
+               goto err_mp_init_primary;
+       }
+
        hw->adapter_state = HNS3_NIC_UNINITIALIZED;
        hns->is_vf = false;
        hw->data = eth_dev->data;
@@ -5515,7 +5548,12 @@ err_rte_zmalloc:
 
 err_init_pf:
        rte_free(hw->reset.wait_data);
+
 err_init_reset:
+       hns3_mp_uninit_primary();
+
+err_mp_init_primary:
+err_mp_init_secondary:
        eth_dev->dev_ops = NULL;
        eth_dev->rx_pkt_burst = NULL;
        eth_dev->tx_pkt_burst = NULL;
@@ -5568,6 +5606,7 @@ static const struct rte_pci_id pci_id_hns3_map[] = {
        { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
        { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
        { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
+       { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
        { .vendor_id = 0, /* sentinel */ },
 };