#define HNS3_DEV_ID_100G_VF 0xA22E
#define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
+/* PCI Config offsets */
+#define HNS3_PCI_REVISION_ID 0x08
+#define HNS3_PCI_REVISION_ID_LEN 1
+
+#define HNS3_PF_FUNC_ID 0
+#define HNS3_1ST_VF_FUNC_ID 1
+
#define HNS3_UC_MACADDR_NUM 128
#define HNS3_VF_UC_MACADDR_NUM 48
#define HNS3_MC_MACADDR_NUM 128
#define HNS3_MAX_BD_SIZE 65535
-#define HNS3_MAX_TX_BD_PER_PKT 8
+#define HNS3_MAX_NON_TSO_BD_PER_PKT 8
+#define HNS3_MAX_TSO_BD_PER_PKT 63
#define HNS3_MAX_FRAME_LEN 9728
#define HNS3_VLAN_TAG_SIZE 4
#define HNS3_DEFAULT_RX_BUF_LEN 2048
+#define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
+#define HNS3_MAX_TSO_HDR_SIZE 512
+#define HNS3_MAX_TSO_HDR_BD_NUM 3
#define HNS3_ETH_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
};
+#define HNS3_PORT_BASE_VLAN_DISABLE 0
+#define HNS3_PORT_BASE_VLAN_ENABLE 1
+struct hns3_port_base_vlan_config {
+ uint16_t state;
+ uint16_t pvid;
+};
+
/* Primary process maintains driver state in main thread.
*
* +---------------+
struct hns3_hw {
struct rte_eth_dev_data *data;
void *io_base;
+ uint8_t revision; /* PCI revision, low byte of class word */
struct hns3_cmq cmq;
struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
uint16_t num_msi;
uint16_t total_tqps_num; /* total task queue pairs of this PF */
uint16_t tqps_num; /* num task queue pairs of this function */
+ uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
uint16_t rss_size_max; /* HW defined max RSS task queue */
uint16_t rx_buf_len;
uint16_t num_tx_desc; /* desc num of per tx queue */
/* The configuration info of RSS */
struct hns3_rss_conf rss_info;
+ bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
uint8_t num_tc; /* Total number of enabled TCs */
uint8_t hw_tc_map;
uint16_t tx_qnum_per_tc; /* TX queue number per TC */
uint32_t flag;
+
+ struct hns3_port_base_vlan_config port_base_vlan_cfg;
/*
* PMD setup and configuration is not thread safe. Since it is not
* performance sensitive, it is better to guarantee thread-safety
uint16_t vlan_id;
};
-struct hns3_port_base_vlan_config {
- uint16_t state;
- uint16_t pvid;
-};
-
/* Vlan tag configuration for RX direction */
struct hns3_rx_vtag_cfg {
uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
struct hns3_pf {
struct hns3_adapter *adapter;
bool is_main_pf;
+ uint16_t func_num; /* num functions of this pf, include pf and vfs */
uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
uint32_t tx_buf_size; /* Tx buffer size for each TC */
bool support_sfp_query;
struct hns3_vtag_cfg vtag_config;
- struct hns3_port_base_vlan_config port_base_vlan_cfg;
LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
struct hns3_fdir_info fdir; /* flow director info */