net/mlx5: fix metadata item validation for ingress flows

[dpdk.git] / drivers / net / hns3 / hns3_ethdev.h

diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index 63e0c2f..3a592c0 100644 (file)
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -6,13 +6,17 @@
 #define _HNS3_ETHDEV_H_
 
 #include <sys/time.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
+#include <rte_byteorder.h>
+#include <rte_io.h>
+#include <rte_spinlock.h>
 
 #include "hns3_cmd.h"
 #include "hns3_mbx.h"
 #include "hns3_rss.h"
 #include "hns3_fdir.h"
 #include "hns3_stats.h"
+#include "hns3_tm.h"
 
 /* Vendor ID */
 #define PCI_VENDOR_ID_HUAWEI                   0x19e5
@@ -169,7 +173,7 @@ enum hns3_media_type {
 
 struct hns3_mac {
        uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
-       bool default_addr_setted; /* whether default addr(mac_addr) is setted */
+       bool default_addr_setted; /* whether default addr(mac_addr) is set */
        uint8_t media_type;
        uint8_t phy_addr;
        uint8_t link_duplex  : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
@@ -348,11 +352,11 @@ enum hns3_schedule {
 
 struct hns3_reset_data {
        enum hns3_reset_stage stage;
-       rte_atomic16_t schedule;
+       uint16_t schedule;
        /* Reset flag, covering the entire reset process */
-       rte_atomic16_t resetting;
+       uint16_t resetting;
        /* Used to disable sending cmds during reset */
-       rte_atomic16_t disable_cmd;
+       uint16_t disable_cmd;
        /* The reset level being processed */
        enum hns3_reset_level level;
        /* Reset level set, each bit represents a reset level */
@@ -727,6 +731,8 @@ struct hns3_pf {
 
        struct hns3_fdir_info fdir; /* flow director info */
        LIST_HEAD(counters, hns3_flow_counter) flow_counters;
+
+       struct hns3_tm_conf tm_conf;
 };
 
 struct hns3_vf {
@@ -796,6 +802,12 @@ struct hns3_adapter {
 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
        container_of(hw, struct hns3_adapter, hw)
 
+static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw)
+{
+       struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
+       return &adapter->pf;
+}
+
 #define hns3_set_field(origin, mask, shift, val) \
        do { \
                (origin) &= (~(mask)); \
@@ -875,7 +887,7 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
 #define hns3_read_dev(a, reg) \
        hns3_read_reg((a)->io_base, (reg))
 
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define ARRAY_SIZE(x) RTE_DIM(x)
 
 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
        do {                                                            \
@@ -934,7 +946,13 @@ int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
                         enum rte_filter_op filter_op, void *arg);
 bool hns3_is_reset_pending(struct hns3_adapter *hns);
 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
-void hns3_update_link_status(struct hns3_hw *hw);
+void hns3_update_link_status_and_event(struct hns3_hw *hw);
+void hns3_ether_format_addr(char *buf, uint16_t size,
+                       const struct rte_ether_addr *ether_addr);
+int hns3_dev_infos_get(struct rte_eth_dev *eth_dev,
+                      struct rte_eth_dev_info *info);
+void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
+                         uint32_t link_speed, uint8_t link_duplex);
 
 static inline bool
 is_reset_pending(struct hns3_adapter *hns)