#include <sys/time.h>
#include <rte_alarm.h>
+#include "hns3_cmd.h"
+#include "hns3_mbx.h"
+#include "hns3_rss.h"
+#include "hns3_fdir.h"
+#include "hns3_stats.h"
+
/* Vendor ID */
#define PCI_VENDOR_ID_HUAWEI 0x19e5
#define HNS3_DEV_ID_100G_VF 0xA22E
#define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
+/* PCI Config offsets */
+#define HNS3_PCI_REVISION_ID 0x08
+#define HNS3_PCI_REVISION_ID_LEN 1
+
+#define HNS3_PF_FUNC_ID 0
+#define HNS3_1ST_VF_FUNC_ID 1
+
#define HNS3_UC_MACADDR_NUM 128
#define HNS3_VF_UC_MACADDR_NUM 48
#define HNS3_MC_MACADDR_NUM 128
#define HNS3_MAX_BD_SIZE 65535
-#define HNS3_MAX_TX_BD_PER_PKT 8
+#define HNS3_MAX_NON_TSO_BD_PER_PKT 8
+#define HNS3_MAX_TSO_BD_PER_PKT 63
#define HNS3_MAX_FRAME_LEN 9728
-#define HNS3_MIN_FRAME_LEN 64
#define HNS3_VLAN_TAG_SIZE 4
#define HNS3_DEFAULT_RX_BUF_LEN 2048
+#define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
+#define HNS3_MAX_TSO_HDR_SIZE 512
+#define HNS3_MAX_TSO_HDR_BD_NUM 3
+#define HNS3_MAX_LRO_SIZE 64512
#define HNS3_ETH_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
#define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
#define HNS3_DEFAULT_MTU 1500UL
#define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
+#define HNS3_MIN_PKT_SIZE 60
#define HNS3_4_TCS 4
#define HNS3_8_TCS 8
-#define HNS3_MAX_TC_NUM 8
#define HNS3_MAX_PF_NUM 8
#define HNS3_UMV_TBL_SIZE 3072
uint32_t link_speed; /* ETH_SPEED_NUM_ */
};
+struct hns3_fake_queue_data {
+ void **rx_queues; /* Array of pointers to fake RX queues. */
+ void **tx_queues; /* Array of pointers to fake TX queues. */
+ uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
+ uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
+};
+
+#define HNS3_PORT_BASE_VLAN_DISABLE 0
+#define HNS3_PORT_BASE_VLAN_ENABLE 1
+struct hns3_port_base_vlan_config {
+ uint16_t state;
+ uint16_t pvid;
+};
/* Primary process maintains driver state in main thread.
*
uint64_t merge_cnt; /* Total merged in high reset times */
};
-struct hns3_hw;
-struct hns3_adapter;
-
typedef bool (*check_completion_func)(struct hns3_hw *hw);
struct hns3_wait_data {
struct hns3_hw {
struct rte_eth_dev_data *data;
void *io_base;
+ uint8_t revision; /* PCI revision, low byte of class word */
+ struct hns3_cmq cmq;
+ struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
+ struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
+ pthread_t irq_thread_id;
struct hns3_mac mac;
unsigned int secondary_cnt; /* Number of secondary processes init'd. */
+ struct hns3_tqp_stats tqp_stats;
+ /* Include Mac stats | Rx stats | Tx stats */
+ struct hns3_mac_stats mac_stats;
uint32_t fw_version;
uint16_t num_msi;
uint16_t total_tqps_num; /* total task queue pairs of this PF */
uint16_t tqps_num; /* num task queue pairs of this function */
+ uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
uint16_t rss_size_max; /* HW defined max RSS task queue */
- uint16_t rx_buf_len;
uint16_t num_tx_desc; /* desc num of per tx queue */
uint16_t num_rx_desc; /* desc num of per rx queue */
struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
int mc_addrs_num; /* Multicast mac addresses number */
+ /* The configuration info of RSS */
+ struct hns3_rss_conf rss_info;
+ bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
+
uint8_t num_tc; /* Total number of enabled TCs */
uint8_t hw_tc_map;
enum hns3_fc_mode current_mode;
struct hns3_dcb_info dcb_info;
enum hns3_fc_status current_fc_status; /* current flow control status */
struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
- uint16_t alloc_tqps;
- uint16_t alloc_rss_size; /* Queue number per TC */
+ uint16_t used_rx_queues;
+ uint16_t used_tx_queues;
- uint32_t flag;
+ /* Config max queue numbers between rx and tx queues from user */
+ uint16_t cfg_max_queues;
+ struct hns3_fake_queue_data fkq_data; /* fake queue data */
+ uint16_t alloc_rss_size; /* RX queue number per TC */
+ uint16_t tx_qnum_per_tc; /* TX queue number per TC */
+
+ uint32_t capability;
+
+ struct hns3_port_base_vlan_config port_base_vlan_cfg;
/*
* PMD setup and configuration is not thread safe. Since it is not
* performance sensitive, it is better to guarantee thread-safety
uint16_t vlan_id;
};
-struct hns3_port_base_vlan_config {
- uint16_t state;
- uint16_t pvid;
-};
-
/* Vlan tag configuration for RX direction */
struct hns3_rx_vtag_cfg {
uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
struct hns3_pf {
struct hns3_adapter *adapter;
bool is_main_pf;
+ uint16_t func_num; /* num functions of this pf, include pf and vfs */
uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
uint32_t tx_buf_size; /* Tx buffer size for each TC */
bool support_sfp_query;
struct hns3_vtag_cfg vtag_config;
- struct hns3_port_base_vlan_config port_base_vlan_cfg;
LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
+
+ struct hns3_fdir_info fdir; /* flow director info */
+ LIST_HEAD(counters, hns3_flow_counter) flow_counters;
};
struct hns3_vf {
#define HNS3_DEV_SUPPORT_DCB_B 0x0
#define hns3_dev_dcb_supported(hw) \
- hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B)
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
}
+int hns3_buffer_alloc(struct hns3_hw *hw);
+int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
+ enum rte_filter_type filter_type,
+ enum rte_filter_op filter_op, void *arg);
+bool hns3_is_reset_pending(struct hns3_adapter *hns);
+bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
+void hns3_update_link_status(struct hns3_hw *hw);
+
+static inline bool
+is_reset_pending(struct hns3_adapter *hns)
+{
+ bool ret;
+ if (hns->is_vf)
+ ret = hns3vf_is_reset_pending(hns);
+ else
+ ret = hns3_is_reset_pending(hns);
+ return ret;
+}
+
+static inline uint64_t
+hns3_txvlan_cap_get(struct hns3_hw *hw)
+{
+ if (hw->port_base_vlan_cfg.state)
+ return DEV_TX_OFFLOAD_VLAN_INSERT;
+ else
+ return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
+}
+
#endif /* _HNS3_ETHDEV_H_ */
git.droids-corp.org / dpdk.git / blobdiff