};
struct hns3_cfg {
- uint8_t vmdq_vport_num;
uint8_t tc_num;
uint16_t tqp_desc_num;
uint16_t rx_buf_len;
* descriptor, it functions only when firmware report the capability of
* HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.
*/
- uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned;
+ uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_aligned;
};
#define HNS3_FIXED_MAX_TQP_NUM_MODE 0
uint64_t dev_caps_mask;
- struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
+ struct hns3_ptype_table ptype_tbl __rte_cache_aligned;
};
enum {
HNS3_DEV_SUPPORT_COPPER_B,
HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B,
HNS3_DEV_SUPPORT_PTP_B,
+ HNS3_DEV_SUPPORT_TX_PUSH_B,
HNS3_DEV_SUPPORT_INDEP_TXRX_B,
HNS3_DEV_SUPPORT_STASH_B,
HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
#define hns3_dev_ras_imp_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B)
+#define hns3_dev_tx_push_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
+
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
#define HNS3_DEV_PRIVATE_TO_PF(adapter) \
}
/*
- * The optimized function for writing registers used in the '.rx_pkt_burst' and
- * '.tx_pkt_burst' ops implementation function.
+ * The optimized function for writing registers reduces one address addition
+ * calculation, it was used in the '.rx_pkt_burst' and '.tx_pkt_burst' ops
+ * implementation function.
*/
static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
{
- rte_io_wmb();
- rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
+ rte_write32(rte_cpu_to_le_32(value), addr);
}
static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
#define hns3_read_dev(a, reg) \
hns3_read_reg((a)->io_base, (reg))
-#define ARRAY_SIZE(x) RTE_DIM(x)
-
#define NEXT_ITEM_OF_ACTION(act, actions, index) \
do { \
act = (actions) + (index); \