/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2019 Hisilicon Limited.
+ * Copyright(c) 2018-2021 HiSilicon Limited.
*/
#ifndef _HNS3_ETHDEV_H_
#define _HNS3_ETHDEV_H_
-#include <sys/time.h>
+#include <pthread.h>
#include <ethdev_driver.h>
#include <rte_byteorder.h>
#include <rte_io.h>
#include "hns3_fdir.h"
#include "hns3_stats.h"
#include "hns3_tm.h"
+#include "hns3_flow.h"
/* Vendor ID */
#define PCI_VENDOR_ID_HUAWEI 0x19e5
#define HNS3_PF_FUNC_ID 0
#define HNS3_1ST_VF_FUNC_ID 1
+#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
+#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
+
#define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
#define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
#define HNS3_UNLIMIT_PROMISC_MODE 0
#define HNS3_LIMIT_PROMISC_MODE 1
+#define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0
+#define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1
+
#define HNS3_UC_MACADDR_NUM 128
#define HNS3_VF_UC_MACADDR_NUM 48
#define HNS3_MC_MACADDR_NUM 128
#define HNS3_MAX_NON_TSO_BD_PER_PKT 8
#define HNS3_MAX_TSO_BD_PER_PKT 63
#define HNS3_MAX_FRAME_LEN 9728
-#define HNS3_VLAN_TAG_SIZE 4
#define HNS3_DEFAULT_RX_BUF_LEN 2048
#define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
#define HNS3_MAX_TSO_HDR_SIZE 512
#define HNS3_MAX_LRO_SIZE 64512
#define HNS3_ETH_OVERHEAD \
- (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
+ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN * 2)
#define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
#define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
#define HNS3_DEFAULT_MTU 1500UL
uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
uint8_t pgid;
uint32_t bw_limit;
- uint8_t up_to_tc_map; /* user priority maping on the TC */
+ uint8_t up_to_tc_map; /* user priority mapping on the TC */
};
struct hns3_dcb_info {
};
struct hns3_cfg {
- uint8_t vmdq_vport_num;
uint8_t tc_num;
- uint16_t tqp_desc_num;
- uint16_t rx_buf_len;
uint16_t rss_size_max;
uint8_t phy_addr;
uint8_t media_type;
uint16_t umv_space;
};
+struct hns3_set_link_speed_cfg {
+ uint32_t speed;
+ uint8_t duplex : 1;
+ uint8_t autoneg : 1;
+};
+
/* mac media type */
enum hns3_media_type {
HNS3_MEDIA_TYPE_UNKNOWN,
HNS3_MEDIA_TYPE_NONE,
};
+#define HNS3_DEFAULT_QUERY 0
+#define HNS3_ACTIVE_QUERY 1
+
struct hns3_mac {
uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
- bool default_addr_setted; /* whether default addr(mac_addr) is set */
uint8_t media_type;
uint8_t phy_addr;
- uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
- uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
- uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
- uint32_t link_speed; /* ETH_SPEED_NUM_ */
- uint32_t supported_capa; /* supported capability for current media */
+ uint8_t link_duplex : 1; /* RTE_ETH_LINK_[HALF/FULL]_DUPLEX */
+ uint8_t link_autoneg : 1; /* RTE_ETH_LINK_[AUTONEG/FIXED] */
+ uint8_t link_status : 1; /* RTE_ETH_LINK_[DOWN/UP] */
+ uint32_t link_speed; /* RTE_ETH_SPEED_NUM_ */
+ /*
+ * Some firmware versions support only the SFP speed query. In addition
+ * to the SFP speed query, some firmware supports the query of the speed
+ * capability, auto-negotiation capability, and FEC mode, which can be
+ * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD.
+ * This field is used to record the SFP information query mode.
+ * Value range:
+ * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY
+ *
+ * - HNS3_DEFAULT_QUERY
+ * Speed obtained is from SFP. When the queried speed changes, the MAC
+ * speed needs to be reconfigured.
+ *
+ * - HNS3_ACTIVE_QUERY
+ * Speed obtained is from MAC. At this time, it is unnecessary for
+ * driver to reconfigured the MAC speed. In addition, more information,
+ * such as, the speed capability, auto-negotiation capability and FEC
+ * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD.
+ */
+ uint8_t query_type;
+ uint32_t supported_speed; /* supported speed for current media type */
uint32_t advertising; /* advertised capability in the local part */
- /* advertised capability in the link partner */
- uint32_t lp_advertising;
+ uint32_t lp_advertising; /* advertised capability in the link partner */
uint8_t support_autoneg;
};
};
enum hns3_reset_level {
- HNS3_NONE_RESET,
+ HNS3_FLR_RESET, /* A VF perform FLR reset */
HNS3_VF_FUNC_RESET, /* A VF function reset */
+
/*
* All VFs under a PF perform function reset.
* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
* same.
*/
HNS3_VF_PF_FUNC_RESET = 2,
+
/*
* All VFs under a PF perform FLR reset.
* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
* In PF FLR, the register state of VF is not reliable, VF's driver
* should not access the registers of the VF device.
*/
- HNS3_VF_FULL_RESET = 3,
- HNS3_FLR_RESET, /* A VF perform FLR reset */
+ HNS3_VF_FULL_RESET,
+
/* All VFs under the rootport perform a global or IMP reset */
HNS3_VF_RESET,
- HNS3_FUNC_RESET, /* A PF function reset */
+
+ /*
+ * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/
+ * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and
+ * can not be changed.
+ */
+
+ HNS3_FUNC_RESET = 5, /* A PF function reset */
+
/* All PFs under the rootport perform a global reset */
HNS3_GLOBAL_RESET,
HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
+ HNS3_NONE_RESET,
HNS3_MAX_RESET
};
struct hns3_wait_data *wait_data;
};
+struct hns3_hw_ops {
+ int (*add_mc_mac_addr)(struct hns3_hw *hw,
+ struct rte_ether_addr *mac_addr);
+ int (*del_mc_mac_addr)(struct hns3_hw *hw,
+ struct rte_ether_addr *mac_addr);
+ int (*add_uc_mac_addr)(struct hns3_hw *hw,
+ struct rte_ether_addr *mac_addr);
+ int (*del_uc_mac_addr)(struct hns3_hw *hw,
+ struct rte_ether_addr *mac_addr);
+ int (*bind_ring_with_vector)(struct hns3_hw *hw, uint16_t vector_id,
+ bool en, enum hns3_ring_type queue_type,
+ uint16_t queue_id);
+};
+
#define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
#define HNS3_INTR_MAPPING_VEC_ALL 1
* enable Rx interrupt.
*
* - HNS3_INTR_MAPPING_VEC_ALL
- * PMD driver can map/unmmap all interrupt vectors with queues When
- * Rx interrupt in enabled.
+ * PMD can map/unmmap all interrupt vectors with queues when
+ * Rx interrupt is enabled.
*/
uint8_t mapping_mode;
/*
uint8_t revision; /* PCI revision, low byte of class word */
struct hns3_cmq cmq;
struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
- struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
- pthread_t irq_thread_id;
struct hns3_mac mac;
+ /*
+ * This flag indicates dev_set_link_down() API is called, and is cleared
+ * by dev_set_link_up() or dev_start().
+ */
+ bool set_link_down;
unsigned int secondary_cnt; /* Number of secondary processes init'd. */
struct hns3_tqp_stats tqp_stats;
/* Include Mac stats | Rx stats | Tx stats */
struct hns3_mac_stats mac_stats;
+ uint32_t mac_stats_reg_num;
struct hns3_rx_missed_stats imissed_stats;
uint64_t oerror_stats;
+ /*
+ * The lock is used to protect statistics update in stats APIs and
+ * periodic task.
+ */
+ rte_spinlock_t stats_lock;
+
uint32_t fw_version;
+ uint16_t pf_vf_if_version; /* version of communication interface */
uint16_t num_msi;
uint16_t total_tqps_num; /* total task queue pairs of this PF */
uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
uint16_t rss_size_max; /* HW defined max RSS task queue */
uint16_t rx_buf_len; /* hold min hardware rx buf len */
- uint16_t num_tx_desc; /* desc num of per tx queue */
- uint16_t num_rx_desc; /* desc num of per rx queue */
uint32_t mng_entry_num; /* number of manager table entry */
uint32_t mac_entry_num; /* number of mac-vlan table entry */
/* The configuration info of RSS */
struct hns3_rss_conf rss_info;
- bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
uint16_t rss_ind_tbl_size;
uint16_t rss_key_size;
uint8_t num_tc; /* Total number of enabled TCs */
uint8_t hw_tc_map;
- enum hns3_fc_mode current_mode;
- enum hns3_fc_mode requested_mode;
+ enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */
struct hns3_dcb_info dcb_info;
enum hns3_fc_status current_fc_status; /* current flow control status */
struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
/*
* vlan mode.
* value range:
- * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHFIT_AND_DISCARD_MODE
+ * HNS3_SW_SHIFT_AND_DISCARD_MODE/HNS3_HW_SHIFT_AND_DISCARD_MODE
*
* - HNS3_SW_SHIFT_AND_DISCARD_MODE
* For some versions of hardware network engine, because of the
- * hardware limitation, PMD driver needs to detect the PVID status
- * to work with haredware to implement PVID-related functions.
+ * hardware limitation, PMD needs to detect the PVID status
+ * to work with hardware to implement PVID-related functions.
* For example, driver need discard the stripped PVID tag to ensure
* the PVID will not report to mbuf and shift the inserted VLAN tag
* to avoid port based VLAN covering it.
*
* - HNS3_HW_SHIT_AND_DISCARD_MODE
- * PMD driver does not need to process PVID-related functions in
+ * PMD does not need to process PVID-related functions in
* I/O process, Hardware will adjust the sequence between port based
* VLAN tag and BD VLAN tag automatically and VLAN tag stripped by
* PVID will be invisible to driver. And in this mode, hns3 is able
uint8_t drop_stats_mode;
uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
+ /*
+ * udp checksum mode.
+ * value range:
+ * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE
+ *
+ * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE
+ * In this mode, HW can not do checksum for special UDP port like
+ * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel
+ * packets without the RTE_MBUF_F_TX_TUNEL_MASK in the mbuf. So, PMD need
+ * do the checksum for these packets to avoid a checksum error.
+ *
+ * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE
+ * In this mode, HW does not have the preceding problems and can
+ * directly calculate the checksum of these UDP packets.
+ */
+ uint8_t udp_cksum_mode;
struct hns3_port_base_vlan_config port_base_vlan_cfg;
+
+ pthread_mutex_t flows_lock; /* rte_flow ops lock */
+ struct hns3_fdir_rule_list flow_fdir_list; /* flow fdir rule list */
+ struct hns3_rss_filter_list flow_rss_list; /* flow RSS rule list */
+ struct hns3_flow_mem_list flow_list;
+
+ struct hns3_hw_ops ops;
+
/*
* PMD setup and configuration is not thread safe. Since it is not
* performance sensitive, it is better to guarantee thread-safety
enum hns3_mp_req_type {
HNS3_MP_REQ_START_RXTX = 1,
HNS3_MP_REQ_STOP_RXTX,
+ HNS3_MP_REQ_START_TX,
+ HNS3_MP_REQ_STOP_TX,
HNS3_MP_REQ_MAX
};
-/* Pameters for IPC. */
+/* Parameters for IPC. */
struct hns3_mp_param {
enum hns3_mp_req_type type;
int port_id;
* The next fields used to calc packet-type by the
* L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor.
*/
- uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM];
+ uint32_t l3table[HNS3_L3TBL_NUM];
uint32_t l4table[HNS3_L4TBL_NUM];
- uint32_t inner_l2table[HNS3_L2TBL_NUM];
uint32_t inner_l3table[HNS3_L3TBL_NUM];
uint32_t inner_l4table[HNS3_L4TBL_NUM];
- uint32_t ol2table[HNS3_OL2TBL_NUM];
uint32_t ol3table[HNS3_OL3TBL_NUM];
uint32_t ol4table[HNS3_OL4TBL_NUM];
* descriptor, it functions only when firmware report the capability of
* HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.
*/
- uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned;
+ uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_aligned;
};
#define HNS3_FIXED_MAX_TQP_NUM_MODE 0
uint8_t tc_max; /* max number of tc driver supported */
uint8_t local_max_tc; /* max number of local tc */
uint8_t pfc_max;
- uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
uint16_t pause_time;
bool support_fc_autoneg; /* support FC autonegotiate */
+ bool support_multi_tc_pause;
uint16_t wanted_umv_size;
uint16_t max_umv_size;
bool support_sfp_query;
uint32_t fec_mode; /* current FEC mode for ethdev */
+ bool ptp_enable;
+
+ /* Stores timestamp of last received packet on dev */
+ uint64_t rx_timestamp;
+
struct hns3_vtag_cfg vtag_config;
LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
struct hns3_tm_conf tm_conf;
};
+enum {
+ HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED,
+ HNS3_PF_PUSH_LSC_CAP_SUPPORTED,
+ HNS3_PF_PUSH_LSC_CAP_UNKNOWN
+};
+
struct hns3_vf {
struct hns3_adapter *adapter;
+
+ /* Whether PF support push link status change to VF */
+ uint16_t pf_push_lsc_cap;
+
+ /*
+ * If PF support push link status change, VF still need send request to
+ * get link status in some cases (such as reset recover stage), so use
+ * the req_link_info_cnt to control max request count.
+ */
+ uint16_t req_link_info_cnt;
+
+ uint16_t poll_job_started; /* whether poll job is started */
};
struct hns3_adapter {
struct hns3_vf vf;
};
- bool rx_simple_allowed;
- bool rx_vec_allowed;
- bool tx_simple_allowed;
- bool tx_vec_allowed;
-
uint32_t rx_func_hint;
uint32_t tx_func_hint;
- struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
-};
+ uint64_t dev_caps_mask;
+ uint16_t mbx_time_limit_ms; /* wait time for mbx message */
-enum {
- HNS3_IO_FUNC_HINT_NONE = 0,
- HNS3_IO_FUNC_HINT_VEC,
- HNS3_IO_FUNC_HINT_SVE,
- HNS3_IO_FUNC_HINT_SIMPLE,
- HNS3_IO_FUNC_HINT_COMMON
+ struct hns3_ptype_table ptype_tbl __rte_cache_aligned;
};
#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
-#define HNS3_DEV_SUPPORT_DCB_B 0x0
-#define HNS3_DEV_SUPPORT_COPPER_B 0x1
-#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
-#define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
-#define HNS3_DEV_SUPPORT_PTP_B 0x4
-#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
-#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
-#define HNS3_DEV_SUPPORT_STASH_B 0x7
-#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
-#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA
-
-#define hns3_dev_dcb_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
-
-/* Support copper media type */
-#define hns3_dev_copper_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
-
-/* Support UDP GSO offload */
-#define hns3_dev_udp_gso_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
-
-/* Support the queue region action rule of flow directory */
-#define hns3_dev_fd_queue_region_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
-
-/* Support PTP timestamp offload */
-#define hns3_dev_ptp_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
-
-#define hns3_dev_tx_push_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
-
-/* Support to Independently enable/disable/reset Tx or Rx queues */
-#define hns3_dev_indep_txrx_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
-
-#define hns3_dev_stash_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
-
-#define hns3_dev_rxd_adv_layout_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B)
+#define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask"
+
+#define HNS3_DEVARG_MBX_TIME_LIMIT_MS "mbx_time_limit_ms"
+
+enum hns3_dev_cap {
+ HNS3_DEV_SUPPORT_DCB_B,
+ HNS3_DEV_SUPPORT_COPPER_B,
+ HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B,
+ HNS3_DEV_SUPPORT_PTP_B,
+ HNS3_DEV_SUPPORT_TX_PUSH_B,
+ HNS3_DEV_SUPPORT_INDEP_TXRX_B,
+ HNS3_DEV_SUPPORT_STASH_B,
+ HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
+ HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B,
+ HNS3_DEV_SUPPORT_RAS_IMP_B,
+ HNS3_DEV_SUPPORT_TM_B,
+ HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B,
+};
-#define hns3_dev_outer_udp_cksum_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B)
+#define hns3_dev_get_support(hw, _name) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_##_name##_B)
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
#define HNS3_DEV_PRIVATE_TO_PF(adapter) \
(&((struct hns3_adapter *)adapter)->pf)
+#define HNS3_DEV_PRIVATE_TO_VF(adapter) \
+ (&((struct hns3_adapter *)adapter)->vf)
#define HNS3_DEV_HW_TO_ADAPTER(hw) \
container_of(hw, struct hns3_adapter, hw)
return &adapter->pf;
}
+static inline struct hns3_vf *HNS3_DEV_HW_TO_VF(struct hns3_hw *hw)
+{
+ struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
+ return &adapter->vf;
+}
+
#define hns3_set_field(origin, mask, shift, val) \
do { \
(origin) &= (~(mask)); \
}
/*
- * The optimized function for writing registers used in the '.rx_pkt_burst' and
- * '.tx_pkt_burst' ops implementation function.
+ * The optimized function for writing registers reduces one address addition
+ * calculation, it was used in the '.rx_pkt_burst' and '.tx_pkt_burst' ops
+ * implementation function.
*/
static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
{
- rte_io_wmb();
- rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
+ rte_write32(rte_cpu_to_le_32(value), addr);
}
static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
#define hns3_read_dev(a, reg) \
hns3_read_reg((a)->io_base, (reg))
-#define ARRAY_SIZE(x) RTE_DIM(x)
-
#define NEXT_ITEM_OF_ACTION(act, actions, index) \
do { \
act = (actions) + (index); \
} \
} while (0)
-#define MSEC_PER_SEC 1000L
-#define USEC_PER_MSEC 1000L
-
-static inline uint64_t
-get_timeofday_ms(void)
-{
- struct timeval tv;
-
- (void)gettimeofday(&tv, NULL);
-
- return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
-}
-
static inline uint64_t
hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
{
return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
}
+int
+hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
+uint32_t hns3_get_speed_capa(struct hns3_hw *hw);
+
int hns3_buffer_alloc(struct hns3_hw *hw);
-int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
- enum rte_filter_type filter_type,
- enum rte_filter_op filter_op, void *arg);
bool hns3_is_reset_pending(struct hns3_adapter *hns);
bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
-void hns3_update_link_status_and_event(struct hns3_hw *hw);
-void hns3_ether_format_addr(char *buf, uint16_t size,
- const struct rte_ether_addr *ether_addr);
-int hns3_dev_infos_get(struct rte_eth_dev *eth_dev,
- struct rte_eth_dev_info *info);
+void hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query);
void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
uint32_t link_speed, uint8_t link_duplex);
-void hns3_parse_devargs(struct rte_eth_dev *dev);
+void hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported);
+
+int hns3_restore_ptp(struct hns3_adapter *hns);
+int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev,
+ struct rte_eth_conf *conf);
+int hns3_ptp_init(struct hns3_hw *hw);
+int hns3_timesync_enable(struct rte_eth_dev *dev);
+int hns3_timesync_disable(struct rte_eth_dev *dev);
+int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp,
+ uint32_t flags __rte_unused);
+int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
+ struct timespec *timestamp);
+int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts);
+int hns3_timesync_write_time(struct rte_eth_dev *dev,
+ const struct timespec *ts);
+int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
+int hns3_eth_dev_priv_dump(struct rte_eth_dev *dev, FILE *file);
static inline bool
is_reset_pending(struct hns3_adapter *hns)
return ret;
}
-static inline uint64_t
-hns3_txvlan_cap_get(struct hns3_hw *hw)
-{
- if (hw->port_base_vlan_cfg.state)
- return DEV_TX_OFFLOAD_VLAN_INSERT;
- else
- return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
-}
-
#endif /* _HNS3_ETHDEV_H_ */