net/hns3: fix Rx/Tx errors stats

[dpdk.git] / drivers / net / hns3 / hns3_ethdev.h

diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index b23c90e..8d6b8cd 100644 (file)
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -6,7 +6,6 @@
 #define _HNS3_ETHDEV_H_
 
 #include <sys/time.h>
-#include <rte_alarm.h>
 #include <rte_ethdev_driver.h>
 
 #include "hns3_cmd.h"
@@ -170,7 +169,7 @@ enum hns3_media_type {
 
 struct hns3_mac {
        uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
-       bool default_addr_setted; /* whether default addr(mac_addr) is setted */
+       bool default_addr_setted; /* whether default addr(mac_addr) is set */
        uint8_t media_type;
        uint8_t phy_addr;
        uint8_t link_duplex  : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
@@ -379,12 +378,11 @@ struct hns3_reset_data {
 #define HNS3_INTR_MAPPING_VEC_RSV_ONE          0
 #define HNS3_INTR_MAPPING_VEC_ALL              1
 
-#define HNS3_INTR_COALESCE_NON_QL              0
-#define HNS3_INTR_COALESCE_QL                  1
-
 #define HNS3_INTR_COALESCE_GL_UINT_2US         0
 #define HNS3_INTR_COALESCE_GL_UINT_1US         1
 
+#define HNS3_INTR_QL_NONE                      0
+
 struct hns3_queue_intr {
        /*
         * interrupt mapping mode.
@@ -405,21 +403,6 @@ struct hns3_queue_intr {
         *     Rx interrupt in enabled.
         */
        uint8_t mapping_mode;
-       /*
-        * interrupt coalesce mode.
-        * value range:
-        *      HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL
-        *
-        *  - HNS3_INTR_COALESCE_NON_QL
-        *     For some versions of hardware network engine, hardware doesn't
-        *     support QL(quanity limiter) algorithm for interrupt coalesce
-        *     of queue's interrupt.
-        *
-        *  - HNS3_INTR_COALESCE_QL
-        *     In this mode, hardware support QL(quanity limiter) algorithm for
-        *     interrupt coalesce of queue's interrupt.
-        */
-       uint8_t coalesce_mode;
        /*
         * The unit of GL(gap limiter) configuration for interrupt coalesce of
         * queue's interrupt.
@@ -427,6 +410,8 @@ struct hns3_queue_intr {
         *      HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
         */
        uint8_t gl_unit;
+       /* The max QL(quantity limiter) value */
+       uint16_t int_ql_max;
 };
 
 #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM          0
@@ -758,6 +743,8 @@ struct hns3_adapter {
                struct hns3_vf vf;
        };
 
+       struct rte_eth_dev *eth_dev;
+
        bool rx_simple_allowed;
        bool rx_vec_allowed;
        bool tx_simple_allowed;
@@ -806,12 +793,8 @@ struct hns3_adapter {
 
 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
        (&((struct hns3_adapter *)adapter)->hw)
-#define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
-       ((struct hns3_adapter *)adapter)
 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
        (&((struct hns3_adapter *)adapter)->pf)
-#define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
-       (&((struct hns3_adapter *)adapter)->vf)
 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
        container_of(hw, struct hns3_adapter, hw)
 
@@ -827,6 +810,8 @@ struct hns3_adapter {
 #define hns3_get_bit(origin, shift) \
        hns3_get_field((origin), (0x1UL << (shift)), (shift))
 
+#define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask))
+
 /*
  * upper_32_bits - return bits 32-63 of a number
  * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
@@ -952,6 +937,8 @@ int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
 bool hns3_is_reset_pending(struct hns3_adapter *hns);
 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
 void hns3_update_link_status(struct hns3_hw *hw);
+void hns3_ether_format_addr(char *buf, uint16_t size,
+                       const struct rte_ether_addr *ether_addr);
 
 static inline bool
 is_reset_pending(struct hns3_adapter *hns)