#define _HNS3_ETHDEV_H_
#include <sys/time.h>
-#include <rte_alarm.h>
+#include <rte_ethdev_driver.h>
#include "hns3_cmd.h"
#include "hns3_mbx.h"
#define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
#define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
+#define HNS3_UNLIMIT_PROMISC_MODE 0
+#define HNS3_LIMIT_PROMISC_MODE 1
+
#define HNS3_UC_MACADDR_NUM 128
#define HNS3_VF_UC_MACADDR_NUM 48
#define HNS3_MC_MACADDR_NUM 128
#define HNS3_HIP08_MIN_TX_PKT_LEN 33
#define HNS3_HIP09_MIN_TX_PKT_LEN 9
+#define HNS3_BITS_PER_BYTE 8
+
#define HNS3_4_TCS 4
#define HNS3_8_TCS 8
};
struct hns3_tc_queue_info {
- uint8_t tqp_offset; /* TQP offset from base TQP */
- uint8_t tqp_count; /* Total TQPs */
- uint8_t tc; /* TC index */
+ uint16_t tqp_offset; /* TQP offset from base TQP */
+ uint16_t tqp_count; /* Total TQPs */
+ uint8_t tc; /* TC index */
bool enable; /* If this TC is enable or not */
};
struct hns3_mac {
uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
- bool default_addr_setted; /* whether default addr(mac_addr) is setted */
+ bool default_addr_setted; /* whether default addr(mac_addr) is set */
uint8_t media_type;
uint8_t phy_addr;
uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
* of the reset level and the one defined in kernel driver should be
* same.
+ *
+ * According to the protocol of PCIe, FLR to a PF resets the PF state as
+ * well as the SR-IOV extended capability including VF Enable which
+ * means that VFs no longer exist.
+ *
+ * In PF FLR, the register state of VF is not reliable, VF's driver
+ * should not access the registers of the VF device.
*/
HNS3_VF_FULL_RESET = 3,
HNS3_FLR_RESET, /* A VF perform FLR reset */
#define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
#define HNS3_INTR_MAPPING_VEC_ALL 1
-#define HNS3_INTR_COALESCE_NON_QL 0
-#define HNS3_INTR_COALESCE_QL 1
-
#define HNS3_INTR_COALESCE_GL_UINT_2US 0
#define HNS3_INTR_COALESCE_GL_UINT_1US 1
+#define HNS3_INTR_QL_NONE 0
+
struct hns3_queue_intr {
/*
* interrupt mapping mode.
* Rx interrupt in enabled.
*/
uint8_t mapping_mode;
- /*
- * interrupt coalesce mode.
- * value range:
- * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL
- *
- * - HNS3_INTR_COALESCE_NON_QL
- * For some versions of hardware network engine, hardware doesn't
- * support QL(quanity limiter) algorithm for interrupt coalesce
- * of queue's interrupt.
- *
- * - HNS3_INTR_COALESCE_QL
- * In this mode, hardware support QL(quanity limiter) algorithm for
- * interrupt coalesce of queue's interrupt.
- */
- uint8_t coalesce_mode;
/*
* The unit of GL(gap limiter) configuration for interrupt coalesce of
* queue's interrupt.
* HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
*/
uint8_t gl_unit;
+ /* The max QL(quantity limiter) value */
+ uint16_t int_ql_max;
};
#define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
* is enabled.
*/
uint8_t vlan_mode;
+ /*
+ * promisc mode.
+ * value range:
+ * HNS3_UNLIMIT_PROMISC_MODE/HNS3_LIMIT_PROMISC_MODE
+ *
+ * - HNS3_UNLIMIT_PROMISC_MODE
+ * In this mode, TX unicast promisc will be configured when promisc
+ * is set, driver can receive all the ingress and outgoing traffic.
+ * In the words, all the ingress packets, all the packets sent from
+ * the PF and other VFs on the same physical port.
+ *
+ * - HNS3_LIMIT_PROMISC_MODE
+ * In this mode, TX unicast promisc is shutdown when promisc mode
+ * is set. So, driver will only receive all the ingress traffic.
+ * The packets sent from the PF and other VFs on the same physical
+ * port won't be copied to the function which has set promisc mode.
+ */
+ uint8_t promisc_mode;
uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
struct hns3_port_base_vlan_config port_base_vlan_cfg;
#define HNS3_L2TBL_NUM 4
#define HNS3_L3TBL_NUM 16
#define HNS3_L4TBL_NUM 16
+#define HNS3_OL2TBL_NUM 4
#define HNS3_OL3TBL_NUM 16
#define HNS3_OL4TBL_NUM 16
struct hns3_ptype_table {
- uint32_t l2table[HNS3_L2TBL_NUM];
- uint32_t l3table[HNS3_L3TBL_NUM];
+ uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM];
uint32_t l4table[HNS3_L4TBL_NUM];
uint32_t inner_l2table[HNS3_L2TBL_NUM];
uint32_t inner_l3table[HNS3_L3TBL_NUM];
uint32_t inner_l4table[HNS3_L4TBL_NUM];
+ uint32_t ol2table[HNS3_OL2TBL_NUM];
uint32_t ol3table[HNS3_OL3TBL_NUM];
uint32_t ol4table[HNS3_OL4TBL_NUM];
};
+#define HNS3_FIXED_MAX_TQP_NUM_MODE 0
+#define HNS3_FLEX_MAX_TQP_NUM_MODE 1
+
struct hns3_pf {
struct hns3_adapter *adapter;
bool is_main_pf;
uint16_t func_num; /* num functions of this pf, include pf and vfs */
+ /*
+ * tqp_config mode
+ * tqp_config_mode value range:
+ * HNS3_FIXED_MAX_TQP_NUM_MODE,
+ * HNS3_FLEX_MAX_TQP_NUM_MODE
+ *
+ * - HNS3_FIXED_MAX_TQP_NUM_MODE
+ * There is a limitation on the number of pf interrupts available for
+ * on some versions of network engines. In this case, the maximum
+ * queue number of pf can not be greater than the interrupt number,
+ * such as pf of network engine with revision_id 0x21. So the maximum
+ * number of queues must be fixed.
+ *
+ * - HNS3_FLEX_MAX_TQP_NUM_MODE
+ * In this mode, the maximum queue number of pf has not any constraint
+ * and comes from the macro RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF
+ * in the config file. Users can modify the macro according to their
+ * own application scenarios, which is more flexible to use.
+ */
+ uint8_t tqp_config_mode;
+
uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
uint32_t tx_buf_size; /* Tx buffer size for each TC */
uint32_t dv_buf_size; /* Dv buffer size for each TC */
struct hns3_err_msix_intr_stats abn_int_stats;
bool support_sfp_query;
+ uint32_t fec_mode; /* current FEC mode for ethdev */
struct hns3_vtag_cfg vtag_config;
LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
struct hns3_vf vf;
};
+ struct rte_eth_dev *eth_dev;
+
bool rx_simple_allowed;
bool rx_vec_allowed;
bool tx_simple_allowed;
#define HNS3_DEV_SUPPORT_DCB_B 0x0
#define HNS3_DEV_SUPPORT_COPPER_B 0x1
#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
-#define HNS3_DEV_SUPPORT_ADQ_B 0x3
+#define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
#define HNS3_DEV_SUPPORT_PTP_B 0x4
#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
#define hns3_dev_udp_gso_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
-/* Support Application Device Queue */
-#define hns3_dev_adq_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B)
+/* Support the queue region action rule of flow directory */
+#define hns3_dev_fd_queue_region_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
/* Support PTP timestamp offload */
#define hns3_dev_ptp_supported(hw) \
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
-#define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
- ((struct hns3_adapter *)adapter)
#define HNS3_DEV_PRIVATE_TO_PF(adapter) \
(&((struct hns3_adapter *)adapter)->pf)
-#define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
- (&((struct hns3_adapter *)adapter)->vf)
#define HNS3_DEV_HW_TO_ADAPTER(hw) \
container_of(hw, struct hns3_adapter, hw)
#define hns3_get_bit(origin, shift) \
hns3_get_field((origin), (0x1UL << (shift)), (shift))
+#define hns3_gen_field_val(mask, shift, val) (((val) << (shift)) & (mask))
+
/*
* upper_32_bits - return bits 32-63 of a number
* A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
#define BIT(nr) (1UL << (nr))
+#define BIT_ULL(x) (1ULL << (x))
+
#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
#define GENMASK(h, l) \
(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
bool hns3_is_reset_pending(struct hns3_adapter *hns);
bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
void hns3_update_link_status(struct hns3_hw *hw);
+void hns3_ether_format_addr(char *buf, uint16_t size,
+ const struct rte_ether_addr *ether_addr);
static inline bool
is_reset_pending(struct hns3_adapter *hns)
git.droids-corp.org / dpdk.git / blobdiff