#ifndef _HNS3_ETHDEV_H_
#define _HNS3_ETHDEV_H_
+#include <pthread.h>
#include <sys/time.h>
#include <ethdev_driver.h>
#include <rte_byteorder.h>
#define HNS3_PF_FUNC_ID 0
#define HNS3_1ST_VF_FUNC_ID 1
+#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
+#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
+
#define HNS3_SW_SHIFT_AND_DISCARD_MODE 0
#define HNS3_HW_SHIFT_AND_DISCARD_MODE 1
uint16_t umv_space;
};
+struct hns3_set_link_speed_cfg {
+ uint32_t speed;
+ uint8_t duplex : 1;
+ uint8_t autoneg : 1;
+};
+
/* mac media type */
enum hns3_media_type {
HNS3_MEDIA_TYPE_UNKNOWN,
HNS3_MEDIA_TYPE_NONE,
};
+#define HNS3_DEFAULT_QUERY 0
+#define HNS3_ACTIVE_QUERY 1
+
struct hns3_mac {
uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
bool default_addr_setted; /* whether default addr(mac_addr) is set */
uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
uint32_t link_speed; /* ETH_SPEED_NUM_ */
- uint32_t supported_capa; /* supported capability for current media */
+ /*
+ * Some firmware versions support only the SFP speed query. In addition
+ * to the SFP speed query, some firmware supports the query of the speed
+ * capability, auto-negotiation capability, and FEC mode, which can be
+ * selected by the 'query_type' filed in the HNS3_OPC_GET_SFP_INFO CMD.
+ * This field is used to record the SFP information query mode.
+ * Value range:
+ * HNS3_DEFAULT_QUERY/HNS3_ACTIVE_QUERY
+ *
+ * - HNS3_DEFAULT_QUERY
+ * Speed obtained is from SFP. When the queried speed changes, the MAC
+ * speed needs to be reconfigured.
+ *
+ * - HNS3_ACTIVE_QUERY
+ * Speed obtained is from MAC. At this time, it is unnecessary for
+ * driver to reconfigured the MAC speed. In addition, more information,
+ * such as, the speed capability, auto-negotiation capability and FEC
+ * mode, can be obtained by the HNS3_OPC_GET_SFP_INFO CMD.
+ */
+ uint8_t query_type;
+ uint32_t supported_speed; /* supported speed for current media type */
uint32_t advertising; /* advertised capability in the local part */
- /* advertised capability in the link partner */
- uint32_t lp_advertising;
+ uint32_t lp_advertising; /* advertised capability in the link partner */
uint8_t support_autoneg;
};
};
enum hns3_reset_level {
- HNS3_NONE_RESET,
+ HNS3_FLR_RESET, /* A VF perform FLR reset */
HNS3_VF_FUNC_RESET, /* A VF function reset */
+
/*
* All VFs under a PF perform function reset.
* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
* same.
*/
HNS3_VF_PF_FUNC_RESET = 2,
+
/*
* All VFs under a PF perform FLR reset.
* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
* In PF FLR, the register state of VF is not reliable, VF's driver
* should not access the registers of the VF device.
*/
- HNS3_VF_FULL_RESET = 3,
- HNS3_FLR_RESET, /* A VF perform FLR reset */
+ HNS3_VF_FULL_RESET,
+
/* All VFs under the rootport perform a global or IMP reset */
HNS3_VF_RESET,
- HNS3_FUNC_RESET, /* A PF function reset */
+
+ /*
+ * The enumeration value of HNS3_FUNC_RESET/HNS3_GLOBAL_RESET/
+ * HNS3_IMP_RESET/HNS3_NONE_RESET are also used by firmware, and
+ * can not be changed.
+ */
+
+ HNS3_FUNC_RESET = 5, /* A PF function reset */
+
/* All PFs under the rootport perform a global reset */
HNS3_GLOBAL_RESET,
HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
+ HNS3_NONE_RESET,
HNS3_MAX_RESET
};
uint8_t revision; /* PCI revision, low byte of class word */
struct hns3_cmq cmq;
struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
- struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
struct hns3_mac mac;
unsigned int secondary_cnt; /* Number of secondary processes init'd. */
struct hns3_tqp_stats tqp_stats;
uint8_t num_tc; /* Total number of enabled TCs */
uint8_t hw_tc_map;
- enum hns3_fc_mode current_mode;
- enum hns3_fc_mode requested_mode;
+ enum hns3_fc_mode requested_fc_mode; /* FC mode requested by user */
struct hns3_dcb_info dcb_info;
enum hns3_fc_status current_fc_status; /* current flow control status */
struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
uint8_t udp_cksum_mode;
struct hns3_port_base_vlan_config port_base_vlan_cfg;
+
+ pthread_mutex_t flows_lock; /* rte_flow ops lock */
+
/*
* PMD setup and configuration is not thread safe. Since it is not
* performance sensitive, it is better to guarantee thread-safety
uint32_t rx_func_hint;
uint32_t tx_func_hint;
+ uint64_t dev_caps_mask;
+
struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
};
#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
-#define HNS3_DEV_SUPPORT_DCB_B 0x0
-#define HNS3_DEV_SUPPORT_COPPER_B 0x1
-#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
-#define HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B 0x3
-#define HNS3_DEV_SUPPORT_PTP_B 0x4
-#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
-#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
-#define HNS3_DEV_SUPPORT_STASH_B 0x7
-#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
-#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA
+#define HNS3_DEVARG_DEV_CAPS_MASK "dev_caps_mask"
+
+enum {
+ HNS3_DEV_SUPPORT_DCB_B,
+ HNS3_DEV_SUPPORT_COPPER_B,
+ HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B,
+ HNS3_DEV_SUPPORT_PTP_B,
+ HNS3_DEV_SUPPORT_INDEP_TXRX_B,
+ HNS3_DEV_SUPPORT_STASH_B,
+ HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
+ HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B,
+ HNS3_DEV_SUPPORT_RAS_IMP_B,
+};
#define hns3_dev_dcb_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
#define hns3_dev_copper_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
-/* Support UDP GSO offload */
-#define hns3_dev_udp_gso_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
-
/* Support the queue region action rule of flow directory */
#define hns3_dev_fd_queue_region_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B)
#define hns3_dev_ptp_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
-#define hns3_dev_tx_push_supported(hw) \
- hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
-
/* Support to Independently enable/disable/reset Tx or Rx queues */
#define hns3_dev_indep_txrx_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
#define hns3_dev_outer_udp_cksum_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B)
+#define hns3_dev_ras_imp_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RAS_IMP_B)
+
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
#define HNS3_DEV_PRIVATE_TO_PF(adapter) \
}
/*
- * The optimized function for writing registers used in the '.rx_pkt_burst' and
- * '.tx_pkt_burst' ops implementation function.
+ * The optimized function for writing registers reduces one address addition
+ * calculation, it was used in the '.rx_pkt_burst' and '.tx_pkt_burst' ops
+ * implementation function.
*/
static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
{
- rte_io_wmb();
- rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
+ rte_write32(rte_cpu_to_le_32(value), addr);
}
static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
#define hns3_read_dev(a, reg) \
hns3_read_reg((a)->io_base, (reg))
-#define ARRAY_SIZE(x) RTE_DIM(x)
-
#define NEXT_ITEM_OF_ACTION(act, actions, index) \
do { \
act = (actions) + (index); \
#define MSEC_PER_SEC 1000L
#define USEC_PER_MSEC 1000L
-static inline uint64_t
-get_timeofday_ms(void)
-{
- struct timeval tv;
-
- (void)gettimeofday(&tv, NULL);
-
- return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
-}
+void hns3_clock_gettime(struct timeval *tv);
+uint64_t hns3_clock_calctime_ms(struct timeval *tv);
+uint64_t hns3_clock_gettime_ms(void);
static inline uint64_t
hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
git.droids-corp.org / dpdk.git / blobdiff