#define _HNS3_ETHDEV_H_
#include <sys/time.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
+#include <rte_byteorder.h>
+#include <rte_io.h>
+#include <rte_spinlock.h>
#include "hns3_cmd.h"
#include "hns3_mbx.h"
#include "hns3_rss.h"
#include "hns3_fdir.h"
#include "hns3_stats.h"
+#include "hns3_tm.h"
/* Vendor ID */
#define PCI_VENDOR_ID_HUAWEI 0x19e5
#define HNS3_UNLIMIT_PROMISC_MODE 0
#define HNS3_LIMIT_PROMISC_MODE 1
+#define HNS3_SPECIAL_PORT_SW_CKSUM_MODE 0
+#define HNS3_SPECIAL_PORT_HW_CKSUM_MODE 1
+
#define HNS3_UC_MACADDR_NUM 128
#define HNS3_VF_UC_MACADDR_NUM 48
#define HNS3_MC_MACADDR_NUM 128
uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
uint32_t link_speed; /* ETH_SPEED_NUM_ */
+ uint32_t supported_capa; /* supported capability for current media */
+ uint32_t advertising; /* advertised capability in the local part */
+ /* advertised capability in the link partner */
+ uint32_t lp_advertising;
+ uint8_t support_autoneg;
};
struct hns3_fake_queue_data {
struct hns3_reset_data {
enum hns3_reset_stage stage;
- rte_atomic16_t schedule;
+ uint16_t schedule;
/* Reset flag, covering the entire reset process */
- rte_atomic16_t resetting;
+ uint16_t resetting;
/* Used to disable sending cmds during reset */
- rte_atomic16_t disable_cmd;
+ uint16_t disable_cmd;
/* The reset level being processed */
enum hns3_reset_level level;
/* Reset level set, each bit represents a reset level */
#define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0
#define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1
+#define HNS3_PKTS_DROP_STATS_MODE1 0
+#define HNS3_PKTS_DROP_STATS_MODE2 1
+
struct hns3_hw {
struct rte_eth_dev_data *data;
void *io_base;
struct hns3_tqp_stats tqp_stats;
/* Include Mac stats | Rx stats | Tx stats */
struct hns3_mac_stats mac_stats;
+ struct hns3_rx_missed_stats imissed_stats;
+ uint64_t oerror_stats;
uint32_t fw_version;
uint16_t num_msi;
* port won't be copied to the function which has set promisc mode.
*/
uint8_t promisc_mode;
+
+ /*
+ * drop_stats_mode mode.
+ * value range:
+ * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2
+ *
+ * - HNS3_PKTS_DROP_STATS_MODE1
+ * This mode for kunpeng920. In this mode, port level imissed stats
+ * is supported. It only includes RPU drop stats.
+ *
+ * - HNS3_PKTS_DROP_STATS_MODE2
+ * This mode for kunpeng930. In this mode, imissed stats and oerrors
+ * stats is supported. Function level imissed stats is supported. It
+ * includes RPU drop stats in VF, and includes both RPU drop stats
+ * and SSU drop stats in PF. Oerror stats is also supported in PF.
+ */
+ uint8_t drop_stats_mode;
+
uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
+ /*
+ * udp checksum mode.
+ * value range:
+ * HNS3_SPECIAL_PORT_HW_CKSUM_MODE/HNS3_SPECIAL_PORT_SW_CKSUM_MODE
+ *
+ * - HNS3_SPECIAL_PORT_SW_CKSUM_MODE
+ * In this mode, HW can not do checksum for special UDP port like
+ * 4789, 4790, 6081 for non-tunnel UDP packets and UDP tunnel
+ * packets without the PKT_TX_TUNEL_MASK in the mbuf. So, PMD need
+ * do the checksum for these packets to avoid a checksum error.
+ *
+ * - HNS3_SPECIAL_PORT_HW_CKSUM_MODE
+ * In this mode, HW does not have the preceding problems and can
+ * directly calculate the checksum of these UDP packets.
+ */
+ uint8_t udp_cksum_mode;
struct hns3_port_base_vlan_config port_base_vlan_cfg;
/*
#define HNS3_FLAG_TC_BASE_SCH_MODE 1
#define HNS3_FLAG_VNET_BASE_SCH_MODE 2
-struct hns3_err_msix_intr_stats {
- uint64_t mac_afifo_tnl_int_cnt;
- uint64_t ppu_mpf_abn_int_st2_msix_cnt;
- uint64_t ssu_port_based_pf_int_cnt;
- uint64_t ppp_pf_abnormal_int_cnt;
- uint64_t ppu_pf_abnormal_int_msix_cnt;
-
- uint64_t imp_tcm_ecc_int_cnt;
- uint64_t cmdq_mem_ecc_int_cnt;
- uint64_t imp_rd_poison_int_cnt;
- uint64_t tqp_int_ecc_int_cnt;
- uint64_t msix_ecc_int_cnt;
- uint64_t ssu_ecc_multi_bit_int_0_cnt;
- uint64_t ssu_ecc_multi_bit_int_1_cnt;
- uint64_t ssu_common_ecc_int_cnt;
- uint64_t igu_int_cnt;
- uint64_t ppp_mpf_abnormal_int_st1_cnt;
- uint64_t ppp_mpf_abnormal_int_st3_cnt;
- uint64_t ppu_mpf_abnormal_int_st1_cnt;
- uint64_t ppu_mpf_abn_int_st2_ras_cnt;
- uint64_t ppu_mpf_abnormal_int_st3_cnt;
- uint64_t tm_sch_int_cnt;
- uint64_t qcn_fifo_int_cnt;
- uint64_t qcn_ecc_int_cnt;
- uint64_t ncsi_ecc_int_cnt;
- uint64_t ssu_port_based_err_int_cnt;
- uint64_t ssu_fifo_overflow_int_cnt;
- uint64_t ssu_ets_tcg_int_cnt;
- uint64_t igu_egu_tnl_int_cnt;
- uint64_t ppu_pf_abnormal_int_ras_cnt;
-};
-
/* vlan entry information. */
struct hns3_user_vlan_table {
LIST_ENTRY(hns3_user_vlan_table) next;
#define HNS3_OL2TBL_NUM 4
#define HNS3_OL3TBL_NUM 16
#define HNS3_OL4TBL_NUM 16
+#define HNS3_PTYPE_NUM 256
struct hns3_ptype_table {
+ /*
+ * The next fields used to calc packet-type by the
+ * L3_ID/L4_ID/OL3_ID/OL4_ID from the Rx descriptor.
+ */
uint32_t l2l3table[HNS3_L2TBL_NUM][HNS3_L3TBL_NUM];
uint32_t l4table[HNS3_L4TBL_NUM];
uint32_t inner_l2table[HNS3_L2TBL_NUM];
uint32_t ol2table[HNS3_OL2TBL_NUM];
uint32_t ol3table[HNS3_OL3TBL_NUM];
uint32_t ol4table[HNS3_OL4TBL_NUM];
+
+ /*
+ * The next field used to calc packet-type by the PTYPE from the Rx
+ * descriptor, it functions only when firmware report the capability of
+ * HNS3_CAPS_RXD_ADV_LAYOUT_B and driver enabled it.
+ */
+ uint32_t ptype[HNS3_PTYPE_NUM] __rte_cache_min_aligned;
};
#define HNS3_FIXED_MAX_TQP_NUM_MODE 0
uint16_t max_umv_size;
uint16_t used_umv_size;
- /* Statistics information for abnormal interrupt */
- struct hns3_err_msix_intr_stats abn_int_stats;
-
bool support_sfp_query;
uint32_t fec_mode; /* current FEC mode for ethdev */
struct hns3_fdir_info fdir; /* flow director info */
LIST_HEAD(counters, hns3_flow_counter) flow_counters;
+
+ struct hns3_tm_conf tm_conf;
};
struct hns3_vf {
bool tx_simple_allowed;
bool tx_vec_allowed;
+ uint32_t rx_func_hint;
+ uint32_t tx_func_hint;
+
struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
};
+enum {
+ HNS3_IO_FUNC_HINT_NONE = 0,
+ HNS3_IO_FUNC_HINT_VEC,
+ HNS3_IO_FUNC_HINT_SVE,
+ HNS3_IO_FUNC_HINT_SIMPLE,
+ HNS3_IO_FUNC_HINT_COMMON
+};
+
+#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint"
+#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint"
+
#define HNS3_DEV_SUPPORT_DCB_B 0x0
#define HNS3_DEV_SUPPORT_COPPER_B 0x1
#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
#define HNS3_DEV_SUPPORT_STASH_B 0x7
+#define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9
+#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA
#define hns3_dev_dcb_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
#define hns3_dev_stash_supported(hw) \
hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
+#define hns3_dev_rxd_adv_layout_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B)
+
+#define hns3_dev_outer_udp_cksum_supported(hw) \
+ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B)
+
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
(&((struct hns3_adapter *)adapter)->hw)
#define HNS3_DEV_PRIVATE_TO_PF(adapter) \
#define HNS3_DEV_HW_TO_ADAPTER(hw) \
container_of(hw, struct hns3_adapter, hw)
+static inline struct hns3_pf *HNS3_DEV_HW_TO_PF(struct hns3_hw *hw)
+{
+ struct hns3_adapter *adapter = HNS3_DEV_HW_TO_ADAPTER(hw);
+ return &adapter->pf;
+}
+
#define hns3_set_field(origin, mask, shift, val) \
do { \
(origin) &= (~(mask)); \
#define hns3_read_dev(a, reg) \
hns3_read_reg((a)->io_base, (reg))
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define ARRAY_SIZE(x) RTE_DIM(x)
#define NEXT_ITEM_OF_ACTION(act, actions, index) \
do { \
}
int hns3_buffer_alloc(struct hns3_hw *hw);
-int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
- enum rte_filter_type filter_type,
- enum rte_filter_op filter_op, void *arg);
+int hns3_dev_flow_ops_get(struct rte_eth_dev *dev,
+ const struct rte_flow_ops **ops);
bool hns3_is_reset_pending(struct hns3_adapter *hns);
bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
-void hns3_update_link_status(struct hns3_hw *hw);
+void hns3_update_link_status_and_event(struct hns3_hw *hw);
void hns3_ether_format_addr(char *buf, uint16_t size,
const struct rte_ether_addr *ether_addr);
+int hns3_dev_infos_get(struct rte_eth_dev *eth_dev,
+ struct rte_eth_dev_info *info);
+void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
+ uint32_t link_speed, uint8_t link_duplex);
+void hns3_parse_devargs(struct rte_eth_dev *dev);
static inline bool
is_reset_pending(struct hns3_adapter *hns)
git.droids-corp.org / dpdk.git / blobdiff